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  • 101.
    Fredriksson, Johan
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Nolte, Thomas
    Mälardalen University, Department of Computer Science and Electronics.
    Sjödin, Mikael
    Mälardalen University, Department of Computer Science and Electronics.
    Schmidt, Heinz
    Mälardalen University, Department of Computer Science and Electronics.
    Contract-Based Reusable Worst-Case Execution Time Estimate2007In: Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'07),, 2007, p. 39-46Conference paper (Refereed)
    Abstract [en]

    We present a contract-based technique to achieve reuse of known worst-case execution times (WCET) in conjunction with reuse of software components. For resource constrained systems, or systems where high degree of predictability is needed, classical techniques for WCET-estimation will result in unacceptable overestimation of the execution-time of reusable software components with rich behavior. Our technique allows different WCETs to be associated with subsets of the component behavior. The appropriate WCET for any usage context of the component is selected be means of component contracts over the input domain. In a case-study we illustrate our technique and demonstrate its potential in achieving tight WCET-estimates for reusable components with rich behavior.

  • 102.
    Fredriksson, Johan
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Nolte, Thomas
    Mälardalen University, Department of Computer Science and Electronics.
    Sjödin, Mikael
    Mälardalen University, Department of Computer Science and Electronics.
    Schmidt, Heinz
    Mälardalen University, Department of Computer Science and Electronics.
    Predicting Execution-Time for Variable Behaviour Embedded Real-Time Components2006In: Workshop on Models and Analysis for Automotive Systems (WMAAS'06) in conjunction with the 27th IEEE Real-Time Systems Symposium (RTSS'06), Rio de Janeiro, Brazil, 2006Conference paper (Refereed)
  • 103.
    Fredriksson, Johan
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Nolte, Thomas
    Mälardalen University, Department of Computer Science and Electronics.
    Sjödin, Mikael
    Mälardalen University, Department of Computer Science and Electronics.
    Schmidt, Heinz
    Mälardalen University, Department of Computer Science and Electronics.
    Reusing Worst-Case Execution Time Analysis with Component Contracts2007In: Proceedings of the 9th Real-Time in Sweden (RTiS'07), 2007Conference paper (Refereed)
    Abstract [en]

    We present a contract-based technique to achieve reuse of known worst-case execution times (WCET) in conjunction with reuse of software components. For resource constrained systems, or systems where high degree of predictability is needed, classical techniques for WCET-estimation will result in unacceptable overestimation of the execution-time of reusable software components with rich behavior. Our technique allows different WCETs to be associated with subsets of the component behavior. The appropriate WCET for any usage context of the component is selected be means of component contracts over the input domain. In a case-study we illustrate our technique and demonstrate its potential in achieving tight WCET-estimates for reusable components with rich behavior.

  • 104.
    Hallmans, D.
    et al.
    ABB AB, Ludvika/Västerås, Sweden.
    Sandström, K.
    ABB Corporate Research, Sweden.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Larsson, S.
    SICS, Västerås, Sweden.
    Challenges and opportunities when introducing cloud computing into embedded systems2015In: Proceeding - 2015 IEEE International Conference on Industrial Informatics, INDIN 2015, 2015, p. 454-459Conference paper (Refereed)
    Abstract [en]

    The use of cloud computing in different application areas is growing fast. More and more functions are being moved into the cloud in order to take advantage of cloud computing strengths such as scalability, resources on demand, and usage based cost models. However, most types of embedded systems are still in an early phase of cloud adoption, with a few exceptions found in e.g., data storage and user interfaces. In this paper we present a number of challenges and opportunities when introducing cloud computing into embedded systems. In particular, we look at embedded systems with requirements on timing predictability, i.e., real-time systems. In the paper we conclude that it is possible to move a complete soft real-time system into the cloud. Moreover we see an upcoming development in cloud computing to potentially allow for hard real-time systems to be moved to the cloud. 

  • 105.
    Hallmans, Daniel
    et al.
    ABB, Sweden.
    Jägemar, Marcus
    Ericsson, Sweden.
    Larsson, Stig
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Identifying Evolution Problems for Large Long Term Industrial Evolution Systems2014In: 38TH ANNUAL IEEE INTERNATIONAL COMPUTER SOFTWARE AND APPLICATIONS CONFERENCE WORKSHOPS (COMPSACW 2014), 2014, no 6th, p. 384-389Conference paper (Refereed)
    Abstract [en]

    Large infrastructure systems with a life time of more than 30 years, such as telecommunication or power transmission systems, are difficult to maintain since they suffer from the end-of-life plague of software, hardware and knowledge. Large companies have traditionally tackled this problem successfully, but maybe not with complete efficiency in all cases. We find system evolution to be an increasingly interesting problem as infrastructure becomes more complicated. Our increasingly complex and advanced society demands more of the infrastructure making system evolution an interesting alternative to system replacement. From the point of view of the ISO/IEC 15288 development process we have identified life cycle issues connected to long life time scenarios and the different life cycle stages. In this paper we contribute with a modification of the utilisation and support stage in ISO/IEC 15288 into an evolution stage where a system is not only retired and replaced but rather evolved into the next generation. Using this approach changes the view of system development for this specific type of systems towards a way of incremental development, where new functions can be added at the same time as old legacy parts are replaced with functionally equivalent modules based on new hardware. We have based our solution on the experience from investigations of life cycle issues for two large infrastructure systems.

  • 106.
    Hallmans, Daniel
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Larsson, Stig
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Method for Handling Evolvability in a Complex Embedded System2013Conference paper (Refereed)
    Abstract [en]

    Handling of obsolete software and/or hardware components together with management of function updates in a complex embedded system with an expected life time of more than 30 years can be a very difficult to almost impossible task. This types of challenges can be found in a large number of companies in, for example, the power transmission industry, power plants, aviation etc. In this paper we present the basic steps in a proposed method for handling evolvability in such embedded systems with long expected life cycles. The key elements of the proposed method are the definition of function dependencies, release planning, and test requirements.

  • 107.
    Hallmans, Daniel
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Larsson, Stig
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Industrial Requirements on Evolution of an Embedded System Architecture2013Conference paper (Refereed)
    Abstract [en]

    Management of obsolete software- and hardware-components along with the addition of new components and functionalities in existing embedded systems can be a very difficult or almost impossible task. If there at the same time is a requirement put on the system that it should be in operation for more than 30 years, then the evolution of the embedded system architecture over such a long duration of time will be an even more challenging problem to solve. A large number of different industries, for example the process and power transmission industries, are faced with this type of challenges on a daily basis. The contribution of our research presented in this paper is a set of questions and answers on how it is possible to replace and update an old control system, with examples inherent in process and power transmission applications. We also look at different methods that can be used during the development of new systems such that they will provide a natural support for evolvability, targeting future control system applications.

  • 108.
    Hallmans, Daniel
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB AB, Ludvika, Sweden.
    Sandström, K.
    ABB Corporate Research, Västerås.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Larsson, S.
    SICS, Västerås, Sweden.
    Consistent sensor values on a real-time ethernet network2016In: IEEE International Workshop on Factory Communication Systems - Proceedings, WFCS, 2016, article id Article number 7496499Conference paper (Refereed)
    Abstract [en]

    Industrial control systems often exhibit a need for short latencies and/or consistent data gathering. In a system with limited resources it is a challenge to achieve the combination of short latencies and consistent data. In this paper we propose three different architectural solutions to this challenge, each having different trade-offs: one that gives a consistent set of data and also a short latency but with a higher resource usage, a second alternative that reduces resource needs but at the cost of an increased latency, and a third and final solution that reduces resource needs to a minimum but in doing so also increasing the latency. The results presented in this paper suggest that it is possible to get low latency and robustness at the cost of performance. 

  • 109.
    Hallmans, Daniel
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB AB, Ludvika, Sweden.
    Sandström, K.
    ABB AB, Västerås, Sweden.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Larsson, Stig
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. SICS, Västerås, Sweden.
    A method and industrial case: Replacement of an FPGA component in a legacy control system2015In: Proceeding - 2015 IEEE International Conference on Industrial Informatics, INDIN 2015, 2015, p. 208-214Conference paper (Refereed)
    Abstract [en]

    A significant part of industrial systems have requirements on long life times. Such requirements on the complete system impose requirements on its corresponding embedded systems to be operational for an equally long time. As a consequence it is of paramount importance to be able to replace obsolete components of the embedded systems during the life time of the system, and to be able to update part of the design due to new requirements. In this paper we present a method to manage component replacement in such systems, and we present an industrial case study highlighting the work needed to replace an FPGA chip with another, including all corresponding legacy FPGA design challenges that comes with such a replacement. We have found one larger problem inherent in the ability to use the included components in a way that is not possible with the new circuits replacing the old ones. This problem significantly increased the work needed when performing the conversion and migration from the old design to the new, since parts of the design had to be redesigned from a functional perspective.

  • 110.
    Hallmans, Daniel
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB AB Ludvika, Sweden .
    Sandström, Kristian
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research Västerås, Sweden.
    Lindgren, Markus
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research Västerås, Sweden.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    GPGPU for Industrial Control Systems2013In: 18th IEEE International Conference on Emerging Technologies & Factory Automation ETFA'13, 2013, p. Article number 6648166-Conference paper (Refereed)
    Abstract [en]

    In this work in progress paper we present parts of our ongoing work on using the Graphical Processing Unit (GPU) in the context of Embedded Systems. As a first step we are investigating the possibility to move functions from a Digital Signal Processor (DSP) to a GPU. If it is possible to make such a migration then it would simplify the hardware designs for some embedded systems by removing external hardware and also remove a potential life cycle issue with obsolete components. We are currently designing a test system to be able to compare performance between a legacy control system used today in industry, based on a CPU/DSP combination, to a new design with a CPU/GPU combination. In this setting the pre-filtering of sampled data, previously done in the DSP, is moved to the GPU.

  • 111.
    Hallmans, Daniel
    et al.
    ABB AB, Ludvika.
    Åsberg, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Towards using the Graphics Processing Unit (GPU) for Embedded Systems2012In: IEEE Symposium on Emerging Technologies and Factory Automation, ETFA 2012, 2012, p. Article number: 6489715-Conference paper (Refereed)
    Abstract [en]

    The Graphics Processing Unit (GPU) is becoming a very powerful platform to accelerate graphics and dataparallel compute-intensive applications. It gives a high performance and at the same time it has a low power consumption. This combination is of high performance and low power consumption is useful when it comes to building an embedded system. In this paper we are looking at the possibility to use a combination of CPU and GPU to provide performance metrics that are required in an embedded system. In particular we look at requirements inherent in the process and power industries where we believe that the GPU has the potential to be a useful and natural element in future embedded system architectures.

  • 112.
    Hansson, Hans
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Carlson, Jan
    Mälardalen University, School of Innovation, Design and Engineering.
    Isovic, Damir
    Mälardalen University, School of Innovation, Design and Engineering.
    Lundqvist, Kristina
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Ouimet, Martin
    Mälardalen University, School of Innovation, Design and Engineering.
    Pettersson, Paul
    Mälardalen University, School of Innovation, Design and Engineering.
    Punnekkat, Sasikumar
    Mälardalen University, School of Innovation, Design and Engineering.
    Seceleanu, Cristina
    Mälardalen University, School of Innovation, Design and Engineering.
    Real-Time Systems2010Book (Other academic)
    Abstract [en]

    This is a textbook developed for use in the Master Programme Module E-M.6 "Real-Time Systems" as part of the Postgraduate Distance studies organized by Fraunhofer IESE and the Distance and International Studies Center at the Technical University of Kaiserslauten, Germany.

  • 113.
    Hansson, Hans
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Real-time in embedded systems2017In: Systems, Controls, Embedded Systems, Energy, and Machines, CRC Press , 2017, p. 16-26-16-58Chapter in book (Other academic)
  • 114.
    Hansson, Hans
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Axelsson, Jakob
    Mälardalen University, School of Innovation, Design and Engineering.
    Björkman, Mats
    Mälardalen University, School of Innovation, Design and Engineering.
    Carlson, Jan
    Mälardalen University, School of Innovation, Design and Engineering.
    Crnkovic, Ivica
    Mälardalen University, School of Innovation, Design and Engineering.
    Lisper, Björn
    Mälardalen University, School of Innovation, Design and Engineering.
    Lundqvist, Kristina
    Mälardalen University, School of Innovation, Design and Engineering.
    Norström, Christer
    Mälardalen University, School of Innovation, Design and Engineering.
    Pettersson, Paul
    Mälardalen University, School of Innovation, Design and Engineering.
    Punnekkat, Sasikumar
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    The PROGRESS Centre for Predictable Embedded Software Systems - Half-time report (edited version)2010Report (Other academic)
    Abstract [en]

    Presentation of the achievements and activities within the PROGRESS national strategic research centre 2006-2008

  • 115.
    Hansson, Hans
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Beating the Automotive Code Complexity Challenge2008Conference paper (Refereed)
  • 116.
    Hansson, Hans
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering.
    Real-Time in Networked Embedded Systems2009In: Networked Embedded Systems, CRC Press, Taylor & Francis Group , 2009Chapter in book (Other academic)
  • 117.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Compositional Analysis for the Multi-Resource Server2015In: 20th IEEE International Conference on Emerging Technologies and Factory Automation ETFA'15, Luxembourg, Luxemburg: IEEE , 2015, p. Article number 7301431-Conference paper (Refereed)
    Abstract [en]

    The Multi-Resource Server (MRS) technique has been proposed to enable predictable execution of memory intensive real-time applications on COTS multi-core platforms. It uses resource reservation approaches in the context of CPUbandwidth and memory-bus bandwidth reservations to bound the interference between the applications running on the same core as well as between the applications running on different cores. In this paper we present a complete composable local and global schedulability analysis for the Multi-Resource Server technique. Based on the proposed analysis,we further provide an experimental study that investigates the behaviour of the MRS and identifies the factors that contribute mostly on the overall system performance.

  • 118.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Compositional analysis for the multi-resource server - a technical report.2014Report (Refereed)
    Abstract [en]

    The Multi-Resource Server (MRS) technique has been proposed toenable predictable execution of memory intensive real-time applicationson COTS multi-core platforms. It uses resource reservationapproaches in the context of CPU-bandwidth and memory-busbandwidth reservations to bound the interferences between the applicationsrunning on the same core as well as between the applicationsrunning on different cores. In this paper we present a completecompositional schedulability analysis for the Multi-ResourceServer technique. Based on the proposed analysis, we further providean experimental study that investigates the behaviour of theMRS and identify the factors that contribute mostly on the overallsystem performance.

  • 119.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Mahmud, Nesredin
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    The Multi-Resource Server for Predictable Execution on Multi-core Platforms2014In: Real-Time Technology and Applications - Proceedings, 2014, Vol. October, p. 1-11Conference paper (Refereed)
    Abstract [en]

    In this paper we present an implementation and demonstration of the Multi-Resource Server (MRS) which enables predictable execution of real-time applications on multi-core platforms. The MRS provides temporal isolation both between tasks running on the same core, as well as, between tasks running on different cores. The latter could, without MRS, interfere with each other due to contention on a shared memory bus. We demonstrate that MRS can be used to ”encapsulate” legacy systems and to give them enough resources to fulfill their purpose. In our case study a legacy media-player is integrated with several resource-hungry tasks running at a different core. We show that without MRS the media-player starts to drop frames due to the interference from other tasks; while introduction of MRS alleviates this problem. Another part of our demonstration shows how traditional periodic real-time tasks can be kept schedulable even when tasks with high memory-demand are added to the system.

  • 120.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Slatman, Joris
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Towards Implementing Multi-resource Server on Multi-core Linux Platform2013In: Proceedings of 18th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA2013), 2013, p. Article number 6648167-Conference paper (Refereed)
    Abstract [en]

    In this paper we present our ongoing work on implementing the multi-resource server technology in the Linux operating system running on multi-core architectures. The multiresource server is used to control the access to both CPU and memory bandwidth resources such that the execution of real-time tasks become predictable. We are targeting Legacy applications to be migrated from single to multi-core architectures. We investigate the available techniques and mechanisms that can support our multi-resource servers and we discuss the potential problems that needed to be tackled considering the requirements of legacy applications.

  • 121.
    Iqbal, Zahid
    et al.
    University of Porto.
    Almeida, Luis
    University of Porto.
    Marau, Ricardo
    University of Porto.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Implementing Hierarchical Scheduling on COTS Ethernet Switches Using a Master/Slave Approach2012In: 7th IEEE International Symposium on Industrial Embedded Systems (SIES'12), Conference proceedings, 2012, p. 76-84Conference paper (Refereed)
    Abstract [en]

    Hierarchical scheduling is instrumental to efficiently deploy component-based designs and achieve composability. It allows partitioning resources into multiple levels, hiding the complexity within each partition behind its respective interface. In this paper we focus on the network resource, particularly on Ethernet using ordinary COTS switches, and we show how hierarchical scheduling can be efficiently deployed using a master/slave approach that enforces the temporal properties of the partitions. We use the FTT-SE protocol for being open source and a bandwidth efficient master/slave alternative currently available for real-time communication over Ethernet. We present a response-time analysis for the traffic submitted within each partition and we validate it using experimental results obtained from a prototype implementation. In particular, the results highlight the strong partitioning capabilities of our approach, with full temporal isolation across partitions in different branches of the hierarchy.

  • 122.
    Johansson, Bjarne
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Industrial Automation, Process Control Platform, Västerås, Sweden.
    Leander, Björn
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Industrial Automation, Process Control Platform, Västerås, Sweden.
    Causevic, Aida
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Papadopoulos, Alessandro
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Classification of PROFINET I/O Configurations utilizing Neural Networks2019In: IEEE International Conference on Emerging Technologies and Factory Automation, ETFA, Institute of Electrical and Electronics Engineers Inc. , 2019, p. 1321-1324Conference paper (Refereed)
    Abstract [en]

    In process automation installations, the I/O system connect the field devices to the process controller over a fieldbus, a reliable, real-time capable communication link with signal values cyclical being exchanged with a 10-100 millisecond rate. If a deviation from intended behaviour occurs, analyzing the potentially vast data recordings from the field can be a time consuming and cumbersome task for an engineer. For the engineer to be able to get a full understanding of the problem, knowledge of the used I/O configuration is required. In the problem report, the configuration description is sometimes missing. In such cases it is difficult to use the recorded data for analysis of the problem.In this paper we present our ongoing work towards using neural network models as assistance in the interpretation of an industrial fieldbus communication recording. To show the potential of such an approach we present an example using an industrial setup where fieldbus data is collected and classified. In this context we present an evaluation of the suitability of different neural net configurations and sizes for the problem at hand.

  • 123.
    Kaczynski, Giordano A.
    et al.
    University of Catania, Catania, Italy .
    Lo Bello, Lucia
    University of Catania, Catania, Italy .
    Nolte, Thomas
    Mälardalen University, Department of Computer Science and Electronics.
    Deriving Exact Stochastic Response Times of Periodic Tasks in Hybrid Priority-driven Soft Real-time Systems2007In: Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'07), Patras, Greece, 2007, p. 101-110Conference paper (Refereed)
    Abstract [en]

    The aim of this paper is to allow for hybrid task sets in the context of stochastic real-time analysis. The paper goes beyond previous work by allowing for the presence of aperiodic tasks in the system. Instead of representing a task with a fixed activation period and a Worst-Case Execution Time (WCET), here a task is characterized by an Arrival Profile (AP) and an Execution Time Profile (ETP), both given by random variables with known distributions. Any number of aperiodic tasks, with arbitrary arrival and execution time profiles, can be dealt with. To cope with the unbounded interference introduced by aperiodic tasks in the system, sporadic and aperiodic tasks are encapsulated within servers. The paper presents the calculus for obtaining the exact ETP of servers, which allows us to derive exact response time distributions of periodic tasks. Also, an example is used to show the potential and validity of the proposed approach. 

  • 124.
    Kaczynski, Giordano A.
    et al.
    University of Catania.
    Lo Bello, Lucia
    University of Catania.
    Nolte, Thomas
    Mälardalen University, Department of Computer Science and Electronics.
    Towards stochastic response-time of hierarchically scheduled real-time tasks2006In: IEEE Symposium on Emerging Technologies and Factory Automation, ETFA, 2006, p. 453-456Conference paper (Refereed)
    Abstract [en]

    The growing need for providing real-time system designers with less pessimistic results than the ones given by traditional worst-case analysis motivates several recent works on stochastic analysis methods. This paper deals with the calculation of stochastic Response Time Profiles of tasks that are hierarchically scheduled using server-based techniques in a stochastic analysis framework. Depending on how tasks are scheduled within the server, differences in temporal performance are expected. In the paper, initial results on calculating the Response Time Profiles for these server-scheduled tasks are outlined.

  • 125.
    Keskin, U.
    et al.
    Technische Universiteit Eindhoven.
    Van Den Heuvel, M. M. H. P.
    Technische Universiteit Eindhoven.
    Bril, R. J.
    Technische Universiteit Eindhoven.
    Lukkien, J. J.
    Technische Universiteit Eindhoven.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    An engineering approach to synchronization based on overrun for compositional real-time systems2011In: SIES 2011 - 6th IEEE International Symposium on Industrial Embedded Systems, Conference Proceedings, 2011, p. 274-283Conference paper (Refereed)
    Abstract [en]

    Hierarchical scheduling frameworks (HSFs) provide means for composing complex real-time systems from well-defined independently developed and analyzed subsystems. To support shared logical resources requiring mutual exclusive access in two-level HSFs, overrun without payback has been proposed as a mechanism to prevent budget depletion during resource access arbitrated by the stack resource policy (SRP). In this paper, we revisit the global schedulability analysis of synchronization protocols based on SRP and overrun without payback for fixed-priority scheduled HSFs. We derive a new global schedulability analysis based on the observation that the overrun budget is merely meant to prevent budget depletion during global resource access. The deadline of a subsystem therefore only needs to hold for its normal budget rather than the sum of the normal and overrun budget. Our novel analysis is considerably simpler than an earlier, initially improved analysis, which improved both the original local and global schedulability analyses. We evaluate the new analysis based on an extensive simulation study and compare the results with the existing analysis. Our simplified analysis does not significantly affect schedulability compared to the initially improved analysis. It is therefore proposed as a preferable engineering approach to synchronization protocols for compositional real-time systems. We accordingly present the implementation of our improvement in an OSEK-compliant real-time operating system to sketch its applicability in today's industrial automotive standards. Both implementation and run-time overheads are discussed providing measured results1. © 2011 IEEE.

  • 126.
    Keskin, Ugur
    et al.
    Technische Universiteit Eindhoven.
    J. Bril, Reinder
    Technische Universiteit Eindhoven.
    Lukkien, Johan
    Technische Universiteit Eindhoven.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Improving the global schedulability analysis of overrun without payback2010In: Proceedings of the Work-In-Progress (WIP) session of the 22nd Euromicro Conference on Real-Time Systems (ECRTS'10) / [ed] Robert I. Davis, 2010Conference paper (Refereed)
    Abstract [en]

    Overrun without payback has been proposed asa mechanism for a stack resource policy (SRP) based synchronizationprotocol for hierarchical scheduling frameworks(HSFs). In this paper we reconsider the global schedulabilityanalysis of an HSF based on two-level fixed-priority preemptivescheduling (FPPS) using overrun without payback asa mechanism. Improved analysis is presented based on theobservation that there is no need to guarantee the overrunbudget before the end of the budget period, because thatadditional amount of resources is only meant to prevent depletionof a budget during global resource access. The resultingimprovement is illustrated by means of an example. Thepossibility to discard the remainder of an overrun budget upona replenishment is briefly considered as a further improvementand its potential is shown using the same example.

  • 127.
    Khalilzad, Nima
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ashjaei, Mohammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, Luis
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. IT/DEEC/University of Porto, Portugal.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Adaptive Multi-Resource End-to-End Reservations for Component-Based Distributed Real-Time Systems2015In: ESTIMedia 2015 - 13th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2015, p. Article number 7351772-Conference paper (Refereed)
    Abstract [en]

    Complexity in the real-time embedded softwaredomain has been growing rapidly. The component-based softwaredevelopment approach facilitates the development process of suchsoftware systems by dividing a complex system into a numberof simpler components. Resource reservation techniques havebeen widely used for providing resources to real-time softwarecomponents. In this paper we target real-time components operatingon a distributed resource infrastructure. Furthermore,we target a class of software components which demonstratedynamic resource consumption behavior. A prime example ofsuch components is a multimedia software component. In thepaper, we present a framework supporting multi-resource endto-end resource reservations. We reserve resource bandwidths onboth processor resources as well as on the network resources. Theproposed framework utilizes a Multiple Input Multiple Output(MIMO) controller which adjusts the sizes of reservations trackingthe dynamic resource demands of the software components. Finally, we present a case study using a multimedia component todemonstrate the performance and efficiency of our framework.

  • 128.
    Khalilzad, Nima
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ashjaei, Mohammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, Luis
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. University of Porto, Portugal.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Towards Adaptive Resource Reservations for Component-Based Distributed Real-Time Systems2015In: ACM SIGBED Review - Special Issue on the 7th Workshop on Adaptive and Reconfigurable Embedded Systems (APRES 2015), 2015, p. 24-27Conference paper (Refereed)
    Abstract [en]

    —In this paper we present our ongoing work on developing a framework supporting adaptive resource reservations targeting component-based distributed real-time systems. The components may be spread over different resources in a distributed system. The proposed framework utilizes a reservationbased scheduling technique in which the sizes of reservations are adjusted during run-time to deal with dynamic resource demands of the software components. We present our modeling approach, we describe design options made and we present corresponding challenges.

  • 129.
    Khalilzad, Nima
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    An Adaptive Scheduling Framework for Component-Based Real-Time Systems2015Report (Other academic)
  • 130.
    Khalilzad, Nima
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    On Component-Based Software Development for Multiprocessor Real-Time Systems2015In: Proceedings - IEEE 21st International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2015, 2015, p. 132-140Conference paper (Refereed)
    Abstract [en]

    Component-based software development providesa modular approach to develop complex software systems. In the context of real-time systems, it is desirable to abstract the timing properties of software components using an interface foreach component. The timing properties of the whole system, composed of multiple components, is studied using the component interfaces. In this paper we focus on periodic interface models. In the case of components developed for single processor platforms, for examining the system schedulability, the interfaces can be regarded as periodic tasks. Thus, making it possible to use the conventional schedulability analyses for the system level schedulability test. In the case of components developed formultiprocessors, since interfaces may have utilization larger than 100 % of a single processor, it is not possible to directly use the component interfaces for the system schedulability test. There-fore, the interfaces have to be decomposed before performing thesystem level schedulability test. In this paper, we target the special case of partitioned EDF for scheduling the components integrated on a multiprocessor. Therefore, the system level schedulability test is equivalent to finding a feasible allocation of component interfaces on the multiprocessor. We propose two algorithms for allocating the multiprocessor periodic interfaces. In addition, we propose anorthogonal approach for developing component-based real-timesystems on multiprocessors in which components with utilizationmore than 100 % of a single processor are divided into smaller subcomponents before abstracting their interfaces. We show, through extensive evaluations, that our alternative approach significantly reduces the interface overhead.

  • 131.
    Khalilzad, Nima
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Faragardi, Hamid Reza
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Towards Energy-Aware Placement of Real-Time Virtual Machines in a Cloud Data Center2015In: Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015, 2015, p. 1657-1662Conference paper (Refereed)
    Abstract [en]

    Cloud computing is an evolving paradigm which is becoming an adoptable technology for a variety of applications. However, cloud infrastructures must be able to fulfill application requirements before adopting cloud solutions. Cloud infrastructure providers communicate the characteristics of their services to their customers through Service Level Agreements (SLA). In order for a real-time application to be able to use cloud technology, cloud infrastructure providers have to be able to provide timing guarantees in the SLAs. In this paper, we present our ongoing work regarding a cloud solution in which periodic tasks are provided as a service in the Software as a Service (SaS) model. Tasks belonging to a certain application are mapped in a Virtual Machine (VM). We also study the problem of VMplacement on a cloud infrastructure. We propose a placement mechanism which minimizes the energy consumption of the data center by consolidating VMs in a minimum number of servers while respecting the timing requirement of virtual machines.

  • 132.
    Khalilzad, Nima
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Kong, Fanxin
    McGill University, Canada.
    Liu, Xue
    McGill University, Canada.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Feedback Scheduling Framework for Component-Based Soft Real-Time Systems2015In: 21th IEEE Real-Time and Embedded Technology and Applications Symposium RTAS'15, 2015, p. 182-193Conference paper (Refereed)
    Abstract [en]

    Component-based software systems with real-time requirements are often scheduled using processor reservation techniques. Such techniques have mainly evolved around hard real-time systems in which worst-case resource demands are considered for the reservations. In soft real-time systems, reserv- ing the processors based on the worst-case demands results in unnecessary over-allocations. In this paper, targeting soft real-time systems running on multiprocessor platforms, we focus on components for which processor demand varies during run-time. We propose a feedback scheduling frameworkwhere processor reservations are used for scheduling components. The reservation bandwidths as well as the reservation periods are adapted using MIMO LQR controllers. We provide an allocation mechanism for distributing components over processors. The proposed framework is implemented in the TrueTime simulation tool for system identification. We use a case study to investigate the performance of our framework in the simulation tool. Finally, the framework is implemented in the Linux kernel for practical evaluations. The evaluation results suggest that the framework can efficiently adapt the reservation parameters during run-time by imposing negligible overhead.

  • 133.
    Khalilzad, Nima Moghaddami
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Towards adaptive hierarchical scheduling of overloaded real-time systems2011In: SIES 2011 - 6th IEEE International Symposium on Industrial Embedded Systems, Conference Proceedings, 2011, p. 39-42Conference paper (Refereed)
    Abstract [en]

    In a hierarchical scheduling framework, a resource can be shared among modules with different criticality levels. In our recently introduced adaptive hierarchical scheduling framework, modules receive a dynamic portion of the CPU during run-time. While providing temporal isolation is one of the main advantages of hierarchical scheduling, in an adaptive framework, for example when the CPU is overloaded, the higher priority modules can violate timing guarantees of the lower priority modules. However, the priorities of modules are assigned based on parameters other than the module criticality levels. For example the priority is often assigned according to periods and deadlines of tasks to increase the CPU utilization assuming static systems, i.e. modules parameters do not change during runtime. In an overload situation the high criticality modules should be superior to the low criticality modules in receiving resources. In this paper, extending our adaptive framework, we propose two techniques for controlling the CPU distribution among modules in an overload situation. We are taking another step towards having a complete adaptive hierarchical scheduling framework by incorporating an overload controller into our framework.

  • 134.
    Kienle, Holger
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Kraft, Johan
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    System-specific static code analyses: a case study in the complex embedded systems domain2012In: Software quality journal, ISSN 0963-9314, E-ISSN 1573-1367, Vol. 20, no 2, p. 337-367Article in journal (Refereed)
    Abstract [en]

    In this paper, we are exploring the approach to utilize system-specific static analyses of code with the goal to improve software quality forspecific software systems. Specialized analyses, tailored for a particular system, make it possible to take advantage of system/domainknowledge that is not available to more generic analyses. Furthermore, analyses can be selected and/or developed in order to best meet the challenges and specific issues of the system at hand. As a result, such analyses can be used as a complement to more generic code analysistools because they are likely to have a better impact on (business) concerns such as improving certain software quality attributes and reducing certain classes of failures. We present a case study of a large, industrial embedded system, giving examples of what kinds of analyses could be realized and demonstrate the feasibility of implementing such analyses. We synthesize lessons learned based on our case study and provide recommendations on how to realize system-specific analyses and how to get them adopted by industry.

  • 135.
    Kienle, Holger
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Kraft, Johan
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    System-specific Static Code Analyses for Complex Embedded Systems2010Conference paper (Refereed)
  • 136.
    Kraft, Johan
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Kienle, Holger
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Crnkovic, Ivica
    Mälardalen University, School of Innovation, Design and Engineering.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering.
    Software Maintenance Research in the PROGRESS Project for Predictable Embedded Software Systems2011In: 15th European Conference on Software Maintenance and Reengineering (CSMR'11) / [ed] Mens, T; Kanellopoulos, Y; Winter, A, Los Alamitos: IEEE Computer Society, 2011, p. 335-338Conference paper (Refereed)
    Abstract [en]

    PROGRESS is a project and strategic research centre at Malardalen University in Sweden that is funded for 2006-2010 by the Swedish Foundation for Strategic Research (SSF). PROGRESS research targets embedded software in the vehicular, automation, and telecom domains, focusing on the areas of component technology, verification and analysis for predictability, predictable execution, as well as reuse and maintenance of legacy embedded software. We first describe the funding, organization and research areas of PROGRESS, and then give several examples of PROGRESS research that addresses maintenance of legacy embedded software with the goal to improve program comprehension, quality assurance, and debugging. Specifically, we describe research in tracing and trace visualization, impact analysis of temporal behavior, slicing, and system-specific static analyses.

  • 137.
    Kraft, Johan
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Continuous Constant-Memory Monitoring of Embedded Software Timing2011In: 2nd International Workshop on Analysis Tools and Methodologies for Embedded and Real-time Systems (WATERS'11), satellite workshop of EUROMICRO Conference on Real-Time Systems (ECRTS'11), 2011Conference paper (Refereed)
    Abstract [en]

    A method is presented for generating statistical models of timing data continuously over very long monitoring sessions. This method is intended for memory-efficient runtime modeling of timing properties in embedded software systems, such as execution times or inter-arrival times, but is a quite generic method that should be applicable for other purposes and domains as well. Specifically, we intend to use this method as a component in automatic generation of simulation models for probabilistic timing analysis of complex embedded software systems. Given a stream of data as input, this method gradually builds up a statistical model capturing the approximate distribution of the data. The method uses a modest and fixed amount of on-target RAM, decided by the desired accuracy of the model, and allows for long monitoring sessions covering billions of data points. The paper presents the motivation, algorithm, a prototype implementation and evaluation using real execution time data from an ARM7 microcontroller.

  • 138.
    Lager, Anders
    et al.
    ABB AB, Västerås, Sweden.
    Spampinato, Giacomo
    ABB AB, Västerås, Sweden.
    Papadopoulos, Alessandro
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Towards Reactive Robot Applications in Dynamic Environments2019In: The 24th IEEE Conference on Emerging Technologies and Factory Automation ETFA2019, 2019, p. 1603-1606Conference paper (Refereed)
    Abstract [en]

    Traditionally, industrial robots have been deployed in fairly static environments, to perform highly dedicated tasks. These robots perform with very high precision and throughput. However, nowadays there is an increasing demand for utilizing robots in more dynamic environments, also performing more flexible and less specialized operations — high mix/low volume. Both traditional industrial robots and force-limited robots are used in collaborative, dynamic environments. Such robot applications introduce new challenges when it comes to efficiency and robustness. In this paper, we propose an architecture for reactive multi-robot applications in the context of dynamic environments, and we analyze the main research challenges that must be tackled for its realization. A logistics use case, with robots picking customer orders from the shelves of a warehouse, is used as a running example to support the description of the key challenges.

  • 139.
    Lindgren, M.
    et al.
    ABB Corporate Research, Västerås, Sweden .
    Sandström, K.
    ABB Corporate Research, Västerås, Sweden .
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hallmans, D.
    ABB AB, Ludvika, Sweden.
    Applicability of using internal GPGPUs in industrial control systems2014In: 19th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2014, 2014, p. Article number 7005096-Conference paper (Refereed)
    Abstract [en]

    Industrial control systems are continuously increasing in functionality, connectivity, and levels of integration, and as a consequence they require more computational power. At the same time, these systems have specific requirements related to cost, reliability, timeliness, and thermal power dissipation, which put restrictions on the hardware and software used. Today the high-end embedded CPUs not only provide multiple cores, but also integrated graphics processors (GPU) at close to no additional cost. The use of GPUs for general processing have several potential values in industrial control systems; 1) the added computational power and the high parallelism could pave way for new functionality and 2) the integrated GPU could potentially replace other hardware and thereby reduce the overall cost. In this paper we investigate the applicability of using integrated GPUs in industrial control systems. We do this by evaluating the performance of GPUs with respect to computational problem types and sizes typically found in industrial control systems. In the end we conclude that GPUs are no obvious match for industrial control systems and that several hurdles remain before a wide adoption can be motivated. 

  • 140. Liu, Meng
    et al.
    Becker, Matthias
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A dependency-graph based priority assignment algorithm for real-time traffic over NoCs with shared virtual-channels2016In: IEEE International Workshop on Factory Communication Systems - Proceedings, WFCS, 2016, article id Article number 7496504Conference paper (Refereed)
    Abstract [en]

    The Network-on-Chip (NoC) is the on-chip interconnection medium of choice for modern massively parallel processors and System-on-Chip (SoC) in general. Fixed-priority based preemptive scheduling using virtual-channels is a solution to support real-time communications in on-chip networks. Targeting the priority assignment problem in the context of NoCs, heuristic based priority assignment algorithms are more practical, due to the exponentially increased search space as the number of flows goes up. In our previous work, we have proposed a graph-based heuristic priority assignment algorithm (called GHSA) for NoC communications, where we show that taking the dependencies between flows into account can significantly reduce the search space. However, GHSA only works for NoCs with distinct priorities. Routers in such type of platforms may have a large amount of buffer cost when the number of flows is high. The applicability can thus be limited in reality. One solution to reduce the buffer cost is to allow priority sharing of different flows. In this paper, we propose a dependency-graph based priority assignment algorithm (called eGHSA) targeting NoCs with shared virtual-channels. A number of experiments as well as a case study based on an automotive application are generated, which clearly show that eGHSA improves the efficiency compared to the existing solution in the literature. 

  • 141.
    Liu, Meng
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Becker, Matthias
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Tighter Recursive Calculus to Compute the Worst-Case Traversal Time of Real-Time Traffic over NoCs2017In: 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2017, p. 275-282, article id 7858332Conference paper (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) is a communication subsystem which has been widely utilized in many-core processors and system-on-chips in general. In this paper, we focus on a Round-Robin Arbitration (RRA) based wormhole-switched NoC which is a common architecture used in most of the existing implementations. In order to execute real-time applications on such a NoC based platform, a number of given real-time requirements need to be fulfilled. One of the most typical requirements is schedulability which refers to if real-time packets can be delivered within the given time durations. Timing analysis is a common tool to verify the schedulability of a real-time system. Unfortunately, the existing timing analyses of RRA-based NoCs either provide too pessimistic estimates which results in overly allocated resources, or require a large amount of processing which limits the applicability in reality. Therefore, in this paper, we present an improved timing analysis, aiming to provide more accurate estimates along with acceptable computation time. From the evaluation results, we can clearly observe the improvement achieved by the proposed timing analysis.

  • 142.
    Liu, Meng
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Becker, Matthias
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Buffer-Aware Analysis for Worst-Case Traversal Time of Real-Time Traffic over RRA-based NoCs2017In: Proceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017, 2017, p. 567-575, article id 7912705Conference paper (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) is a communication sub-system which has been widely utilized in many-core processors and system-on-chips in general. In order to execute time-critical applications on a NoC-based platform, the timing behavior of the network needs to be predicted during system design. One of the most important timing requirements is regarding schedulability, which refers to determining if a real-time packet can be delivered within a specific time duration. To verify the fulfillment of such timing requirement, a proper timing analysis is mandatory. Our work focuses on a Round-Robin Arbitration (RRA) based wormhole-switched NoC, which is a common architecture used in many of the existing implementations. Recursive Calculus (RC) is one of the existing analysis approaches for RRA-based NoCs which has been utilized in many research works. However, RC does not take buffer-effects into account. As a result, while performing RC on most of the existing RRA-based NoC designs, it can produce unsafe estimates which is not acceptable for time-critical systems. In this paper, we identify the optimistic problem of RC, and we propose a Revised Recursive Calculus (RRC) which extends RC by considering buffer-effects as well as supporting packetization.

  • 143.
    Liu, Meng
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Becker, Matthias
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Improved Priority Assignment for Real-Time Communications in On-Chip Networks2015In: ACM International Conference Proceeding SeriesVolume 04-06, 2015, p. 171-180Conference paper (Refereed)
    Abstract [en]

    The Network-on-Chip is the on-chip interconnection medium of choice for modern massively parallel processors and System-on-Chip in general. Fixed-priority based preemptive scheduling using virtual-channels is a solution to support real-time communications in on-chip networks. However, the different characteristics of the Network-on-Chip compared to the single processor scheduling problem prevents the usage of known optimal algorithms (e.g. the Audsley's algorithm) to assign priorities to messages. A heuristic search algorithm based approach (called the HSA) focusing on the priority assignment for on-chip communications has been presented in the literature. The HSA is much faster than an exhaustive search based solution, with a price of missing certain schedulable cases (i.e. non-optimal). In this paper, we present two undirected-graph based priority assignment algorithms, the GESA and the GHSA. In contrast to the previous work, we can decrease the search space significantly by taking the interference dependencies of different messages on the network into account. A number of experiments are generated, in order to evaluate the proposed algorithms. The results show that the GESA can always achieve higher schedulability ratios than the HSA, but may require longer processing time. On the other hand, the GHSA has the same performance as the HSA regarding the schedulability, but can significantly improve the efficiency.

  • 144.
    Liu, Meng
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Becker, Matthias
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Scheduling Real-Time Packets with Non-preemptive Regions on Priority-Based NoCs2016In: Proceedings - 2016 IEEE 22nd International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2016, 2016Conference paper (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) is a preferred communi- cation medium for massively parallel platforms. Fixed-priority based scheduling using virtual-channels is one of the promising solutions to support real-time traffic in on-chip networks. Most of the existing NoC implementations which can support fixed- priority based scheduling use a flit-level preemptive scheduling. Under such a mechanism, preemptions can happen between the transmissions of successive flits. In this paper, we present a modified framework where the non-preemptive region of each NoC packet increases from a single flit. Using the proposed approach, the response times of certain packet flows can be reduced, which can thus improve the schedulability of the whole network. As a result, the utilization of NoCs can be improved by admitting more real-time traffic. Schedulability tests regarding the proposed framework are presented along with the proof of the correctness. Moreover, a number of experiments as well as a case study based on an automotive application have been generated, where we can clearly observe the improvement of our solution compared to the original flit-level preemptive NoC.

  • 145.
    Liu, Meng
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Becker, Matthias
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Tighter Time Analysis for Real-Time Traffic in On-Chip Networks with Shared Priorities2016In: 2016 10th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016, 2016, article id 7579319Conference paper (Refereed)
    Abstract [en]

    The Network-on-Chip (NoC) is the preferred inter- connection medium for massively parallel platforms. Targeting real-time applications, fixed-priority based NoCs with virtual- channels have been proposed as a promising solution. In order to verify if specific time requirements can be satisfied, scheduability tests are typically used. Several analysis approaches have been proposed targeting priority-based NoCs. However, due to the approximation considered in the analyses, the results may involve a large amount of pessimism. The applicability of the analyses is thus limited in practice. In this paper, we identify a number of properties of NoCs with shared priorities. An improved time analysis is proposed where pessimism can be significantly reduced for many cases. In order to evaluate the proposed analysis, a number of experiments have been generated along with a case study based on an automotive application. The improvement can be clearly observed from the evaluation results.

  • 146.
    Liu, Meng
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Becker, Matthias
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Using Non-Preemptive Regions and Path Modification to Improve Schedulability of Real-Time Traffic over Priority-Based NoCs2017In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, no 6, p. 886-915Article in journal (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) is a preferred communication medium for massively parallel platforms. Fixed-priority based scheduling using virtual-channels is one of the promising solutions to support real-time traffic in on-chip networks. Most of the existing works regarding priority-based NoCs use a flit-level preemptive scheduling. Under such a mechanism, preemptions can only happen between the transmissions of successive flits but not during the transmission of a single flit. In this paper, we present a modified framework where the non-preemptive region of each NoC packet increases from a single flit. Using the proposed approach, the response times of certain traffic flows can be reduced, which can thus improve the schedulability of the whole network. As a result, the utilization of NoCs can be improved by admitting more real-time traffic. Schedulability tests regarding the proposed framework are presented along with the proof of the correctness. Additionally, we also propose a path modification approach on top of the non-preemptive region based method to further improve schedulability. A number of experiments have been performed to evaluate the proposed solutions, where we can observe significant improvement on schedulability compared to the original flit-level preemptive NoCs. 

  • 147.
    Liu, Meng
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Becker, Matthias
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Using Segmentation to Improve Schedulability of Real-Time Traffic over RRA-based NoCs2016In: ACM SIGBED Review. Special Issue on 14th International Workshop on Real-Time Networks (RTN 2016) SIGBED Review, ISSN 1551-3688, Vol. 13, no 4, p. 20-24Article in journal (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) is the interconnect of choice for many- core processors and system-on-chips in general. Most of the existing NoC designs focus on the performance with respect to average throughput, which makes them less applicable for real-time applications especially when applications have hard timing requirements on the worst-case scenarios. In this paper, we focus on a Round- Robin Arbitration (RRA) based wormhole-switched NoC which is a common architecture used in most of the existing implementations. We propose a novel segmentation algorithm targeting RRA-based NoCs in order to improve the schedulability of real-time traffic without modifying the hardware architecture. According to the evaluation results, the proposed segmentation solution can signifi- cantly improve the schedulability of the whole network.

  • 148.
    Liu, Meng
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Becker, Matthias
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Using Segmentation to Improve Schedulability of RRA-based NoCs with Mixed Traffic2017In: 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2017, p. 744-750, article id 7858413Conference paper (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) is the interconnect of choice for many- core processors and system-on-chips in general. Most of the exist- ing NoC designs focus on the performance with respect to average throughput, which makes them less applicable for real-time appli- cations especially when applications have hard timing requirements on the worst-case scenarios. In this paper, we focus on a Round- Robin Arbitration (RRA) based wormhole-switched NoC which is a common architecture used in most of the existing implementa- tions. We propose a novel segmentation algorithm targeting RRA- based NoCs in order to improve the schedulability of real-time traf- fic without modifying the hardware architecture. Additionally, we also address the problem of transmitting both real-time traffic and best-effort traffic in the same NoC. The proposed solutions aim to provide timing guarantees to real-time traffic and achieve low la- tency for best-effort traffic. According to the evaluation results, the proposed segmentation solution can significantly improve the schedulability of the whole network.

  • 149.
    Liu, Meng
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Kato, Shinpei
    Nagoya University, Nagoya, Japan.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Server-based Approach for Overrun Management in Multi-Core Real-Time Systems2014Conference paper (Refereed)
    Abstract [en]

    This paper presents a server-based framework for task overrun management in multi-core real-time systems. Unlike most existing scheduling methods which usually assume a single upper bound of the Worst-Case Execution Time (WCET) for each task, our approach targets scenarios with task overruns. The main idea of our framework is to employ Synchronized Deferrable Servers (SDS) to deal with globally scheduled task overruns, while a partitioned scheduling approach is applied on regular task executions. Moreover, we provide a deterministic Worst- Case Response Time (WCRT) analysis focusing on hard timing constraints, along with a probabilistic analysis of Deadline Miss Ratio (DMR) for soft real-time applications. In the evaluation phase, we have implemented two types of experiments evaluating different timing constraints. 

  • 150.
    Liu, Meng
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Kato, Shinpei
    Nagoya University, Nagoya, Japan.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    An Adaptive Server-Based Scheduling Framework with Capacity Reclaiming and Borrowing2014In: RTCSA 2014 - 20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2014, p. Article number 6910548-Conference paper (Refereed)
    Abstract [en]

    In this paper, we present a new reservation based scheduling framework for soft real-time systems using EDF algorithm (called CARB-EDF). This framework has the features of Capacity Adaptation, Reclaiming and Borrowing. This framework can simplify the initial configuration of the system, where the system designer does not need to provide any estimations of task execution times. We also present a Chebyshev’s inequality based predictor to estimate task execution times. A number of simulation-based experiments have been implemented. According to the results compared with some related works, our scheduling framework can provide a better performance with acceptable extra scheduling overhead. 

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