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  • 1.
    Afsharmazayejani, R.
    et al.
    Shahid Bahonar University of Kerman, Kerman, Iran.
    Yazdanpanah, F.
    Vali-e-Asr University, Rafsanjan, Iran.
    Rezaei, A.
    Northwestern University, Evanston, United States.
    Alaei, M.
    Vali-e-Asr University, Rafsanjan, Iran.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    HoneyWiN: Novel honeycomb-based wireless NoC architecture in many-core era2018In: Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349, Vol. 10824 LNCS, p. 304-316Article in journal (Refereed)
    Abstract [en]

    Although NoC-based systems with many cores are commercially available, their multi-hop nature has become a bottleneck on scaling performance and energy consumption parameters. Alternatively, hybrid wireless NoC provides a postern by exploiting single-hop express links for long-distance communications. Also, there is a common wisdom that grid-like mesh is the most stable topology in conventional designs. That is why almost all of the emerging architectures had been relying on this topology as well. In this paper, first we challenge the efficiency of the grid-like mesh in emerging systems. Then, we propose HoneyWiN, a hybrid reconfigurable wireless NoC architecture that relies on the honeycomb topology. The simulation results show that on average HoneyWiN saves 17% of energy consumption while increases the network throughput by 10% compared to its wireless mesh counterpart. 

  • 2.
    Akbari, N.
    et al.
    University of Tehran, Tehran, Iran.
    Modarressi, M.
    University of Tehran, Tehran, Iran.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Royal Institute of Technology (KTH), Sweden.
    Loni, Mohammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Royal Institute of Technology (KTH), Sweden.
    A Customized Processing-in-Memory Architecture for Biological Sequence Alignment2018In: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, Institute of Electrical and Electronics Engineers Inc. , 2018, article id 8445124Conference paper (Refereed)
    Abstract [en]

    Sequence alignment is the most widely used operation in bioinformatics. With the exponential growth of the biological sequence databases, searching a database to find the optimal alignment for a query sequence (that can be at the order of hundreds of millions of characters long) would require excessive processing power and memory bandwidth. Sequence alignment algorithms can potentially benefit from the processing power of massive parallel processors due their simple arithmetic operations, coupled with the inherent fine-grained and coarse-grained parallelism that they exhibit. However, the limited memory bandwidth in conventional computing systems prevents exploiting the maximum achievable speedup. In this paper, we propose a processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications. The design is composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture. Experimental results show that the proposed architecture results in up to 2.4x speedup and 41% reduction in power consumption, compared to a processor-side parallel implementation. 

  • 3.
    Ebrahimi, M.
    et al.
    KTH Royal Institute of Technology, Sweden.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A General Methodology on Designing Acyclic Channel Dependency Graphs in Interconnection Networks2018In: IEEE Micro, ISSN 0272-1732, E-ISSN 1937-4143, Vol. 38, no 3, p. 79-85Article in journal (Refereed)
    Abstract [en]

    For the past three decades, the interconnection network has been developed based on two major theories, one by Dally and the other by Duato. In this article, we introduce EbDa with a simplified theoretical basis, which directly allows for designing an acyclic channel dependency graph and verifying algorithms on their freedom from deadlock. EbDa is composed of three theorems that enable extracting all allowable turns without dealing with turn models.

  • 4.
    Ebrahimi, M.
    et al.
    Royal Institute of Technology, Sweden.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Royal Institute of Technology, Sweden.
    EbDa: A new theory on design and verification of deadlock-free interconnection networks2017In: Proceedings - International Symposium on Computer Architecture, Institute of Electrical and Electronics Engineers Inc. , 2017, p. 703-715Conference paper (Refereed)
    Abstract [en]

    Freedom from deadlock is one of the most important issues when designing routing algorithms in on-chip/off-chip networks. Many works have been developed upon Dally's theory proving that a network is deadlock-free if there is no cyclic dependency on the channel dependency graph. However, fnding such acyclic graph has been very challenging, which limits Dally's theory to networks with a low number of channels. In this paper, we introduce three theorems that directly lead to routing algorithms with an acyclic channel dependency graph. We also propose the partitioning methodology, enabling a design to reach the maximum adaptiveness for the n-dimensional mesh and k-ary n-cube topologies with any given number of channels. In addition, deadlock-free routing algorithms can be derived ranging from maximally fully adaptive routing down to deterministic routing. The proposed theorems can drastically remove the diffculties of designing deadlock-free routing algorithms. 

  • 5.
    Ebrahimi, Masoumeh
    et al.
    KTH Royal Inst Technol, Stockholm, Sweden..
    Weldezion, Awet Yemane
    Hangofay AB, Stockholm, Sweden..
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    NoD: Network-on-Die as a Standalone NoC for Heterogeneous Many-core Systems in 2.5D ICs2017In: 2017 19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS), 2017, p. 28-33Conference paper (Refereed)
    Abstract [en]

    Due to a high cost of 3D IC process technology, the semiconductor industry is targeting 2.5D ICs with interposer as a fast and low-cost alternative to integrate dissimilar technologies. In this paper, we propose an independent network-on-chip die, called Network-on-Die (NoD), for 2.5D ICs that operates as a communication backbone for heterogeneous many-core systems on interposer. NoD is responsible for routing packets from a source router to a destination router, and the connections between routers and cores pass through the interposer. This technique eliminates the complexity of the routing algorithms in heterogeneous systems by turning the irregular form of NoC in 2.5D ICs into a regular/optimized one in NoD. The performance evaluation is verified through RTL simulations for a heterogeneous many-core system of varying die sizes and with asymmetric shapes. We provide the theoretical justification for our simulation results.

  • 6.
    Firuzan, A.
    et al.
    Islamic Azad University, Tehran, Iran.
    Modarressi, M.
    University of Tehran and IPM School of ComputerScience, Tehran, Iran.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Reshadi, M.
    Islamic Azad University, Tehran, Iran.
    Reconfigurable Network-on-Chip for 3D Neural Network Accelerators2018In: 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018, Institute of Electrical and Electronics Engineers Inc. , 2018Conference paper (Refereed)
    Abstract [en]

    Parallel hardware accelerators for large-scale neural networks typically consist of several processing nodes, arranged as a multi- or many-core system-on-chip, connected by a network-on-chip (NoC). Recent proposals also benefit from the emerging 3D memory-on-logic architectures to provide sufficient bandwidth for neural networks. Handling the heavy traffic between neurons and memory and also the multicast-based inter-neuron traffic, which often varies over time, is the most challenging design consideration for the networks-on-chip in such accelerators. To address these issues, a reconfigurable network-on-chip architecture for 3D memory-on-logic neural network accelerators is presented in this paper. The reconfigurable NoC can adapt its topology to the on-chip traffic patterns. It can be also configured as a tree-like structure to support multicast-based neuron-to-neuron and memory-to-neuron traffic of neural networks. The evaluation results show that the proposed architecture can better manage the multicast-based traffic of neural networks than some state-of-the-art topologies and considerably increase throughput and power efficiency. 

  • 7.
    Loni, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ahlberg, Carl
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ekström, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Embedded Acceleration of Image Classification Applications for Stereo Vision Systems2018In: Design, Automation & Test in Europe Conference & Exhibition DATE'18, 2018Conference paper (Other academic)
  • 8.
    Loni, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    ADONN: Adaptive Design of Optimized Deep Neural Networks for Embedded Systems2018In: 21st Euromicro Conference on Digital System Design DSD'18, 2018, p. 397-404, article id 8491845Conference paper (Refereed)
    Abstract [en]

    Nowadays, many modern applications, e.g. autonomous system, and cloud data services need to capture and process a big amount of raw data at runtime, that ultimately necessitates a high-performance computing model. Deep Neural Network (DNN) has already revealed its learning capabilities in runtime data processing for modern applications. However, DNNs are becoming more deep sophisticated models for gaining higher accuracy which require a remarkable computing capacity. Considering high-performance cloud infrastructure as a supplier of required computational throughput is often not feasible. Instead, we intend to find a near-sensor processing solution which will lower the need for network bandwidth and increase privacy and power efficiency, as well as guaranteeing worst-case response-times. Toward this goal, we introduce ADONN framework, which aims to automatically design a highly robust DNN architecture for embedded devices as the closest processing unit to the sensors. ADONN adroitly searches the design space to find improved neural architectures. Our proposed framework takes advantage of a multi-objective evolutionary approach, which exploits a pruned design space inspired by a dense architecture. Unlike recent works that mainly have tried to generate highly accurate networks, ADONN also considers the network size factor as the second objective to build a highly optimized network fitting with limited computational resource budgets while delivers comparable accuracy level. In comparison with the best result on CIFAR-10 dataset, a generated network by ADONN presents up to 26.4 compression rate while loses only 4% accuracy. In addition, ADONN maps the generated DNN on the commodity programmable devices including ARM Processor, Hiph-Performance CPU, GPU, and FPGA.

  • 9.
    Loni, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hamouachy, Fadouao
    Casarrubios, Clémentine
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    AutoRIO: An Indoor Testbed for Developing Autonomous Vehicles2019In: International Japan-Africa Conference on Electronics, Communications and Computations JAC-ECC, 2019, p. 69-72Conference paper (Refereed)
    Abstract [en]

    Autonomous vehicles have a great influence on our life. These vehicles are more convenient, more energy efficient providing higher safety level and cheaper driving solutions. In addition, decreasing the generation of CO 2 , and the risk vehicular accidents are other benefits of autonomous vehicles. However, leveraging a full autonomous system is challenging and the proposed solutions are newfound. Providing a testbed for evaluating new algorithms is beneficial for researchers and hardware developers to verify the real impact of their solutions. The existence of testing environment is a low-cost infrastructure leading to increase the time-to-market of novel ideas. In this paper, we propose Auto Rio, a cutting-edge indoor testbed for developing autonomous vehicles.

  • 10.
    Loni, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Majd, Amin
    Åbo Akademi University, Turku, Finland.
    Loni, Abdolah
    KTH Royal Institute of Technology, Stockholm, Sweden.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Troubitsyna, Elena
    KTH Royal Institute of Technology, Stockholm, Sweden.
    Designing Compact Convolutional Neural Network for Embedded Stereo Vision Systems2018In: IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip MCSoC-2018, 2018, p. 244-251, article id 8540240Conference paper (Refereed)
  • 11.
    Maabi, Somayeh
    et al.
    Shahid Beheshti University, Tehran, Iran.
    Safaei, Farshad R.Pour
    Shahid Beheshti University, Tehran, Iran .
    Rezaei, Amin
    University of Louisiana at Lafayette, Lafayette, United States.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Royal Institute of Technology (KTH), Stockholm, Sweden.
    Zhao, Dan
    Old Dominion University, Norfolk, United States .
    ERFAN: Efficient reconfigurable fault-tolerant deflection routing algorithm for 3-D Network-on-Chip2016In: International System on Chip Conference, IEEE Computer Society, 2016, p. 306-311Conference paper (Refereed)
    Abstract [en]

    With degradation in transistors dimensions and complication of circuits, Three-Dimensional Network-on-Chip (3-D NoC) is presented as a promising solution in electronic industry. By increasing the number of system components on a chip, the probability of failure will increase. Therefore, proposing fault tolerance mechanisms is an important target in emerging technologies. In this paper, two efficient fault-tolerant routing algorithms for 3-D NoC are presented. The presented algorithms have significant improvement in performance parameters, in exchange for small area overhead. Simulation results show that even with the presence of faults, the network latency is decreased in comparison with state-of-the-art works. In addition, the network reliability is improved reasonably.

  • 12.
    Majd, A.
    et al.
    Abo Akademi University, Turku, Finland.
    Ashraf, A.
    Abo Akademi University, Turku, Finland.
    Troubitsyna, E.
    Abo Akademi University, Turku, Finland.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Integrating Learning, Optimization, and Prediction for Efficient Navigation of Swarms of Drones2018In: Proceedings - 26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2018, Institute of Electrical and Electronics Engineers Inc. , 2018, p. 101-108Conference paper (Refereed)
    Abstract [en]

    Swarms of drones are increasingly been used in a variety of monitoring and surveillance, search and rescue, and photography and filming tasks. However, despite the growing popularity of swarm-based applications of drones, there is still a lack of approaches to generate efficient drone routes while minimizing the risks of drone collisions. In this paper, we present a novel approach that integrates learning, optimization, and prediction for generating efficient and safe routes for swarms of drones. The proposed approach comprises three main components: (1) a high-performance dynamic evolutionary algorithm for optimizing drone routes, (2) a reinforcement learning algorithm for incorporating the feedback and runtime data about the system state, and (3) a prediction approach to predict the movement of drones and moving obstacles in the flying zone. We also present a parallel implementation of the proposed approach and evaluate it against two benchmarks. The results demonstrate that the proposed approach allows to significantly reduce the route lengths and computation overhead while producing efficient and safe routes. 

  • 13.
    Majd, A.
    et al.
    Åbo Akademi University, Turku, Finland.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Troubitsyna, E.
    Åbo Akademi University, Turku, Finland.
    Sahebi, G.
    University of Turku, Turku, Finland.
    Optimal smart mobile access point placement for maximal coverage and minimal communication2017In: CM International Conference Proceeding Series, Volume Part F130524, Association for Computing Machinery , 2017, Vol. Part F130524, article id a21Conference paper (Refereed)
    Abstract [en]

    A selection of the optimal placements of the access points and sensors constitutes one of the fundamental challenges in the monitoring of spatial phenomena in wireless sensor networks (WSNs). Access points should occupy the best locations in order to obtain a sufficient degree of coverage with a low communication cost. Finding an optimal placement is an NP-hard problem that is further complicated by the real-world conditions such as obstacles, radiation interference etc. In this paper, we propose a compound method to select the best near-optimal placement of SMAPs with the goal to maximize the monitoring coverage and to minimize the communication cost. Our approach combinesa parallel implementation of the Imperialist Competitive Algorithm (ICA) with a greedy method.The benchmarking of the proposed approach demonstrates its clear advantages in solving and optimizing the placement problem. 

  • 14.
    Majd, A.
    et al.
    Åbo Akademi University, Turku, Finland.
    Sahebi, G.
    University of Turku, Turku, Finland.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Troubitsyna, E.
    Åbo Akademi University, Turku, Finland.
    Optimizing scheduling for heterogeneous computing systems using combinatorial meta-heuristic solution2017In: 2017 IEEE SmartWorld Ubiquitous Intelligence and Computing, Advanced and Trusted Computed, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People and Smart City Innovation, SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI 2017 - Conference Proceedings, 2017, p. 1-8Conference paper (Refereed)
    Abstract [en]

    Today, based on fast development especially in Network-on-Chip (NoC)-based many-core systems, the task scheduling problem plays a critical role in high-performance computing. It is an NP-hard problem. The complexity increases further when the scheduling problem is applied to heterogeneous platforms. Exploring the whole search space in order to find the optimal solution is not time efficient, thus metaheuristics are mostly used to find a near-optimal solution in a reasonable amount of time. We propose a compound method to select the best near-optimal task schedule in the heterogeneous platform in order to minimize the execution time. For this, we combine a new parallel meta-heuristic method with a greedy scheme. We introduce a novel metaheuristic method for near-optimal scheduling that can provide performance guarantees for multiple applications implemented on a shared platform. Applications are modeled as directed acyclic task graphs (DAG) for execution on a heterogeneous NoC-based many-core platform with given communication costs. We introduce an order-based encoding especially for pipelined operation that improves (decreases) execution time by more than 46%. Moreover, we present a novel multi-population method inspired by both genetic and imperialist competitive algorithms specialized for the scheduling problem, improving the convergence policy and selection pressure. The potential of the approach is demonstrated by experiments using a Sobel filter, SUSAN filter, RASTA-PLP, and JPEG encoder as real-world case studies. 

  • 15.
    Majd, Amin
    et al.
    Abo Akademi University, Turku, Finland.
    Ashraf, Adnan
    Abo Akademi University, Turku, Finland.
    Troubitsyna, Elena
    Abo Akademi University, Turku, Finland.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Using Optimization, Learning, and Drone Reflexes to Maximize Safety of Swarms of Drones2018In: IEEE Congress on Evolutionary Computation IEEE CEC'18, 2018Conference paper (Refereed)
  • 16.
    Majd, Amin
    et al.
    Åbo Akad Univ, Turku, Finland..
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Plosila, Juha
    Univ Turku, Turku, Finland..
    Khalilzad, Nima
    KTH Royal Inst Technol, Stockholm, Sweden..
    Sahebi, Golnaz
    Univ Turku, Turku, Finland..
    Troubitsyna, Elena
    Åbo Akad Univ, Turku, Finland..
    NOMeS: Near-Optimal Metaheuristic Scheduling for MPSoCs2017In: 2017 19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS), 2017, p. 70-75Conference paper (Refereed)
    Abstract [en]

    The task scheduling problem for Multiprocessor System-on-Chips (MPSoC), which plays a vital role in performance, is an NP-hard problem. Exploring the whole search space in order to find the optimal solution is not time efficient, thus metaheuristics are mostly used to find a near-optimal solution in a reasonable amount of time. We propose a novel metaheuristic method for near-optimal scheduling that can provide performance guarantees for multiple applications implemented on a shared platform. Applications are represented as directed acyclic task graphs (DAG) and are executed on an MPSoC platform with given communication costs. We introduce a novel multi-population method inspired by both genetic and imperialist competitive algorithms. It is specialized for the scheduling problem with the goal to improve the convergence policy and selection pressure. The potential of the approach is demonstrated by experiments using a Sobel filter, a SUSAN filter, RASTA-PLP and JPEG encoder as real-world case studies.

  • 17.
    Majd, Amin
    et al.
    Abo Akad Univ, Finland..
    Sahebi, Golnaz
    Univ Turku, Finland..
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Plosila, Juha
    Univ Turku, Finland..
    Lotfi, Shahriar
    Univ Tabriz, Iran..
    Tenhunen, Hannu
    Univ Turku, inland..
    Parallel imperialist competitive algorithms2018In: Concurrency and Computation, ISSN 1532-0626, E-ISSN 1532-0634, Vol. 30, no 7, article id e4393Article in journal (Refereed)
    Abstract [en]

    The importance of optimization and NP-problem solving cannot be overemphasized. The usefulness and popularity of evolutionary computing methods are also well established. There are various types of evolutionary methods; they are mostly sequential but some of them have parallel implementations as well. We propose a multi-population method to parallelize the Imperialist Competitive Algorithm. The algorithm has been implemented with the Message Passing Interface on 2 computer platforms, and we have tested our method based on shared memory and message passing architectural models. An outstanding performance is obtained, demonstrating that the proposed method is very efficient concerning both speed and accuracy. In addition, compared with a set of existing well-known parallel algorithms, our approach obtains more accurate results within a shorter time period.

  • 18.
    Majd, Amin
    et al.
    Abo Akad Univ, Dept Informat Technol, Turku, Finland..
    Troubitsyna, Elena
    Abo Akad Univ, Dept Informat Technol, Turku, Finland..
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Optimal Placement for Smart Mobile Access Points2018In: 2018 IEEE SMARTWORLD, UBIQUITOUS INTELLIGENCE & COMPUTING, ADVANCED & TRUSTED COMPUTING, SCALABLE COMPUTING & COMMUNICATIONS, CLOUD & BIG DATA COMPUTING, INTERNET OF PEOPLE AND SMART CITY INNOVATION (SMARTWORLD/SCALCOM/UIC/ATC/CBDCOM/IOP/SCI) / [ed] Wang, G Han, Q Bhuiyan, MZA Ma, X Loulergue, F Li, P Roveri, M Chen, L, 2018, p. 1659-1667Conference paper (Refereed)
    Abstract [en]

    Recently Smart Mobile Access Point (SMAP) based architectures have emerged as a promising solution for creating smart solutions supporting monitoring of special phenomena. SMAP allow us to predict communication activities in a system using the information collected from the network, and select the best approach to support the network at any given time. To improve the network performance, SMAPs can autonomously change their positions. They communicate with each other and carry out distributed computing tasks, constituting a mobile fog-computing platform. However, the communication cost becomes a critical factor. In this paper, we propose a compound method to select the best near-optimal placement of SMAPs with the goal to maximize the monitoring coverage and to minimize the communication cost. Our approach combines a parallel implementation of the Imperialist Competitive Algorithm (ICA) with Kruskal's Algorithm.

  • 19.
    Namazi, A.
    et al.
    University of Tehran, Tehran, Iran.
    Abdollahi, M.
    University of Tehran, Tehran, Iran.
    Safari, S.
    University of Tehran, Tehran, Iran.
    Mohammadi, S.
    University of Tehran, Tehran, Iran.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    LRTM: Life-time and Reliability-aware Task Mapping Approach for Heterogeneous Multi-core Systems2018In: 2018 11th International Workshop on Network on Chip Architectures, NoCArc 2018 - In conjunction with the 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018, Institute of Electrical and Electronics Engineers Inc. , 2018, article id 8541223Conference paper (Refereed)
    Abstract [en]

    Technology scaling, increasing number of components in a single chip, and aging effects have brought severe reliability challenges in multi-core platforms. They are more susceptible to faults, both permanent and transient. This paper proposes a Lifetime and Reliability-aware Task Mapping (LRTM) approach to many-core platforms with heterogeneous cores. It tries to confront both transient faults and wear-out failures. Our proposed approach maintains the predefined level of reliability for the task graph in presence of transient faults over the whole lifetime of the system. LRTM uses replication technique with minimum replica overhead, maximum achievable performance, and minimum temperature increase to confront transient faults while increasing the lifetime of the system. Besides, LRTM specifies task migration plans with the minimum overhead using a novel heuristic approach on the occurrence of permanent core failures due to wear-out mechanisms. Task migration scenarios are used during run-time to increase the lifetime of the system while maintaining reliability threshold of the system. Results show the effectiveness of LRTM improves for bigger mesh sizes and higher reliability thresholds. Simulation results obtained from real benchmarks show the proposed approach decreases design-time calculation up to 4371% compared to exhaustive exploration while achieving lifetime negligibly lower than the exhaustive solution (up to 5.83%). LRTM also increases lifetime about 3% compared to other heuristic approaches in the literature.

  • 20.
    Rezaei, A.
    et al.
    Northwestern University (NU), Evanston, IL, United States.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Zhou, H.
    Northwestern University (NU), Evanston, IL, United States.
    Multiobjectivism in Dark Silicon Age2018In: Advances in Computers, vol. 110, Academic Press Inc. , 2018, Vol. 110, p. 83-126Chapter in book (Refereed)
    Abstract [en]

    MCSoCs, with their scalability and parallel computation power, provide an ideal implementation base for modern embedded systems. However, chip designers are facing a design challenge wherein shrinking component sizes though have improved density but started stressing energy budget. This phenomenon, that is called utilization wall, has revolutionized the semiconductor industry by shifting the main purpose of chip design from a performance-driven approach to a complex multiobjective one. The area of the chip which cannot be powered is known as dark silicon. In this chapter, we address the multiobjectivism in dark silicon age. First, we overview state-of-the-art works in a categorized manner. Second, we introduce a NoC-based MCSoC architecture, named shift sprinting, in order to increase overall reliability as well as gain high performance. Third, we explain an application mapping approach, called round rotary mapping, for HWNoC-based MCSoC in order to first balance the usage of wireless links by avoiding congestion over wireless routers and second spread temperature across the whole chip by utilizing dark silicon. Finally, we conclude the chapter by providing a future outlook of dark silicon research trend. 

  • 21.
    Rezaei, A.
    et al.
    Northwestern University, Evanston, United States.
    Zhao, D.
    Old Dominion University, Norfolk, United States.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Royal Institute of Technology (KTH), Sweden.
    Zhou, H.
    Northwestern University, Evanston, United States.
    Multi-objective Task Mapping Approach for Wireless NoC in Dark Silicon Age2017In: Proceedings - 2017 25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2017, Institute of Electrical and Electronics Engineers Inc. , 2017, p. 589-592Conference paper (Refereed)
    Abstract [en]

    Hybrid Wireless Network-on-Chip (HWNoC) provides high bandwidth, low latency and flexible topology configurations, making this emerging technology a scalable communication fabric for future Many-Core System-on-Chips (MCSoCs). On the other hand, dark silicon is dominating the chip footage of upcoming MCSoCs since Dennard scaling fails due to the voltage scaling problem that results in higher power densities. Moreover, congestion avoidance and hot-spot prevention are two important challenges of HWNoC-based MCSoCs in dark silicon age, Therefore, in this paper, a novel task mapping approach for HWNoC is introduced in order to first balance the usage of wireless links by avoiding congestion over wireless routers and second spread temperature across the whole chip by utilizing dark silicon. Simulation results show significant improvement in both congestion and temperature control of the system, compared to state-of-The-Art works. 

  • 22.
    Yazdanpanah, Fahimeh
    et al.
    Vali E Asr Univ, Fac Engn, Dept Comp Engn, Rafsanjan, Iran..
    AfsharMazayejani, Raheel
    Shahid Bahonar Univ, Dept Comp Engn, Fac Engn, Kemran, Iran..
    Alaei, Mohammad
    Vali E Asr Univ, Fac Engn, Dept Comp Engn, Rafsanjan, Iran..
    Rezaei, Amin
    Northwestern Univ, Evanston, IL USA..
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    An energy-efficient partition-based XYZ-planar routing algorithm for a wireless network-on-chip2019In: Journal of Supercomputing, ISSN 0920-8542, E-ISSN 1573-0484, Vol. 75, no 2, p. 837-861Article in journal (Refereed)
    Abstract [en]

    In the current many-core architectures, network-on-chips (NoCs) have been efficiently utilized as communication backbones for enabling massive parallelism and high degree of integration on a chip. In spite of the advantages of conventional NoCs, wired multi-hop links impose limitations on their performance by long delay and much power consumption especially in large systems. To overcome these limitations, different solutions such as using wireless interconnections have been proposed. Utilizing long-range, high bandwidth and low power wireless links can lead to solve the problems corresponding to wired links. Meanwhile, the grid-like mesh is the most stable topology in conventional NoC designs. That is why most of the wireless network-on-chip (WNoC) architectures have been designed based on this topology. The goals of this article are to challenge mesh topology and to demonstrate the efficiency of honeycomb-based WNoC architectures. In this article, we propose HoneyWiN, hybrid wired/wireless NoC architecture with honeycomb topology. Also, a partition-based XYZ-planar routing algorithm for energy conservation is proposed. In order to demonstrate the advantages of the proposed architecture, first, an analytical comparison of HoneyWiN with a mesh-based WNoC, as the baseline architecture, is carried out. In order to compare the proposed architecture, we implement our partition-based routing algorithm in the form of 2-axes coordinate system in the baseline architecture. Simulation results show that HoneyWiN reduces about 17% of energy consumption while increases the throughput by 10% compared to the mesh-based WNoC. Then, HoneyWiN is compared with four state-of-the-art mesh-based NoC architectures. In all of the evaluations, HoneyWiN provides higher performance in term of delay, throughput and energy consumption. Overall, the results indicate that HoneyWiN is very effective in improving throughput, increasing speed and reducing energy consumption.

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