mdh.sePublications
Change search
Refine search result
1 - 31 of 31
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Inam, Rafia
    Ericsson AB, Kista, Sweden.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Survey on Testing for Cyber Physical System2015In: Testing Software and Systems: 27th IFIP WG 6.1 International Conference, ICTSS 2015, Sharjah and Dubai, United Arab Emirates, November 23-25, 2015, Proceedings, 2015, p. 194-207Conference paper (Refereed)
    Abstract [en]

    Cyber Physical Systems (CPS) bridge the cyber-world of computing and communications with the physical world and require development of secure and reliable software. It asserts a big challenge not only on testing and verifying the correctness of all physical and cyber components of such big systems, but also on integration of these components. This paper develops a categorization of multiple levels of testing required to test CPS and makes a comparison of these levels with the levels of software testing based on the V-model. It presents a detailed state-of-the-art survey on the testing approaches performed on the CPS. Further, it provides challenges in CPS testing.

  • 2.
    Behnam, Moris
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Inam, Rafia
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Multi-core Composability in the Face of Memory Bus Contention2012Conference paper (Refereed)
    Abstract [en]

    In this paper we describe the problem of achieving composability of independently developed real-time subsystems to be executed on a multicore platform.We evaluate existing work for achieving real-time performance on multicores and illustrate their lack with respect to composability. To better address composability we present a multi-resource server-based scheduling technique to provide predictable performance when composing multiple subsystems on a multicore platform. To achieve composability also on multicore platforms, we propose to add memory-bandwidth as an additional server resource. Tasks within our multi-resource servers are guaranteed both CPU- and memory-bandwidth; thus the performance of a server will become independent of resource usage by tasks in other servers. We are currently implementing multi-resource servers for the Enea’s OSE operating system for a P4080 8-core processor to be tested with software for a 3G-basestation.

  • 3.
    Inam, Rafia
    Mälardalen University, School of Innovation, Design and Engineering.
    An Introduction to GPGPU Programming - CUDA Architecture2010Report (Other academic)
  • 4.
    Inam, Rafia
    Mälardalen University, School of Innovation, Design and Engineering.
    Different Approaches used in Software Product Families2010Report (Other academic)
    Abstract [en]

    The use of software in consumer products is growing tremendously in current era. Further the complexity of software in products is growing, diversity increasing, and the lead time is decreasing. To meet all these challenges software reuse in consumer products is the solution. This evolves the concepts of software product family, product population, and product lines. Three different approaches are used to integrate all software within hardware. These three approaches are Integration-Oriented platform, Hierarchal and Composition-Oriented. The integration-oriented approach is a classical approach used for many years in industry but unable to meet the challenges of todays increased usage. Hierarchical and Composition-Oriented approaches are popular now-a-days to meet the challenges of industry.

  • 5.
    Inam, Rafia
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hierarchical scheduling for predictable execution of real-time software components and legacy systems2014Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    This dissertation presents techniques to achieve predictable execution of coarse-grained software components and for preservation of temporal properties of components during their integration and reuse.

    The dissertation presents a novel concept runnable virtual node (RVN) which interaction with the environment is bounded both by a functional and a temporal interface, and the validity of its internal temporal behaviour is preserved when integrated with other components or when reused in a new environment. The realization of RVN exploits techniques for hierarchical scheduling to achieve temporal isolation, and the principles from component-based software-engineering to achieve functional isolation. The proof-of-concept case studies executed on a micro-controller demonstrate the preserving of real-time properties within software components for predictable integration and reusability in a new environment, in both hierarchical scheduling and RVN contexts.

    Further, a multi-resource server (MRS) is proposed and implemented to enable predictable execution when composing multiple real-time components on a COTS multicore platform. MRS uses resource reservation for both CPU-bandwidth and memory-bus bandwidth to bound the interferences between tasks running on the same core, as well as, between tasks running on different cores. The later could, without MRS, interfere with each other due to contention on a shared memory-bus and memory. The results indicated that MRS can be used to "encapsulate" legacy systems and to give them enough resources to fulfill their purpose. In the dissertation, the compositional schedulability analysis for MRS is also provided and an experimental study is performed to bring insight on the correlation between the server budgets.

    We believe that the proposed approaches enable a faster software integration and support legacy reuse and that this work transcend the boundaries of software engineering and real-time systems.

  • 6.
    Inam, Rafia
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Performance Preservation using Servers for Predictable Execution and Integration2014In: The 38th Annual International Computers, Software & Applications Conference COMPSAC 2014, 2014, p. 614-617Conference paper (Refereed)
    Abstract [en]

    In real-time embedded systems the components and components integration must satisfy both functional correctness and extra-functional correctness, such as satisfying timing properties. Deploying multiple real-time components on a physical node poses timing problems in components’s integration. These timing problems during integration further effect predictability and reusability of real-time components. We propose a novel concept of runnable virtual node (RVN) whose interaction with the environment is bounded both by a functional and a temporal interface, and the validity of its internal temporal behaviour is preserved when integrated with other components or when reused in a new environment. Our realization of RVN exploits the latest techniques for hierarchical scheduling framework to achieve temporal isolation, and the principles from component-based software-engineering to achieve functional isolation. Proof-of-concept case studies executed on an AVR based 32- bit micro-controller demonstrates the preserving of real-time properties within components for predictable integration and reusability in a new environment without altering its temporal behaviour in both hierarchical scheduling and RVN contexts. We also take a step ahead towards expanding the performance preserving servers’ concept for multicore platform on which the scheduling of real-time tasks is inherently unpredictable due to the contention for shared physical memory and caches. It results in proposing and implementation of a novel type of server, called Multi-Resource Server (MRS) which controls the access to both CPU and memory bandwidth resources such that the execution of real-time tasks become predictable. The MRS provides temporal isolation both between tasks running on the same core, as well as, between tasks running on different cores. Further, we provide the schedulability analysis for MRS to provide predictable performance when composing multiple components on a shared multi-core platform.

  • 7.
    Inam, Rafia
    Mälardalen University, School of Innovation, Design and Engineering.
    Towards a Predictable Component-Based Run-Time System2012Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    In this thesis we propose a technique to preserve the temporal properties of realtime components during their integration and reuse. We propose a new concept of runnable virtual node which is a coarse-grained real-time component that provides functional and temporal isolation with respect to its environment. A virtual node’s interaction with the environment is bounded by both a functional and a temporal interface, and the validity of its internal temporal behaviour is preserved when integrated with other components or when reused in a new environment.

     

    The first major contribution of this thesis is the implementation of a Hierarchical Scheduling Framework (HSF) on an open source real-time operating system (FreeRTOS) with the emphasis of doing minimal changes to the underlying FreeRTOS kernel and keeping its API intact to support the temporal isolation between a numbers of applications, on a single processor. Temporal isolation between the components during runtime prevents failure propagation between different components.

     

    The second contribution of the thesis is with respect to the integration of components, where we first illustrate how the concept of the runnable virtual node can be integrated in several component technologies and, secondly, we perform a proof-of-concept case study for the ProCom component technology where we demonstrate the runnable virtual node’s real-time properties for temporal isolations and reusability.

     

    We have performed experimental evaluations on EVK1100 AVR based 32-bit micro-controller and have checked the system behaviour during heavy-load and over-load situations by visualizing execution traces in both hierarchical scheduling and virtual node contexts. The results for the case study demonstrate temporal error containment within a runnable virtual node as well as reuse of the node in a new environment without altering its temporal behaviour.

  • 8.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Compositional Analysis for the Multi-Resource Server2015In: 20th IEEE International Conference on Emerging Technologies and Factory Automation ETFA'15, Luxembourg, Luxemburg: IEEE , 2015, p. Article number 7301431-Conference paper (Refereed)
    Abstract [en]

    The Multi-Resource Server (MRS) technique has been proposed to enable predictable execution of memory intensive real-time applications on COTS multi-core platforms. It uses resource reservation approaches in the context of CPUbandwidth and memory-bus bandwidth reservations to bound the interference between the applications running on the same core as well as between the applications running on different cores. In this paper we present a complete composable local and global schedulability analysis for the Multi-Resource Server technique. Based on the proposed analysis,we further provide an experimental study that investigates the behaviour of the MRS and identifies the factors that contribute mostly on the overall system performance.

  • 9.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Compositional analysis for the multi-resource server - a technical report.2014Report (Refereed)
    Abstract [en]

    The Multi-Resource Server (MRS) technique has been proposed toenable predictable execution of memory intensive real-time applicationson COTS multi-core platforms. It uses resource reservationapproaches in the context of CPU-bandwidth and memory-busbandwidth reservations to bound the interferences between the applicationsrunning on the same core as well as between the applicationsrunning on different cores. In this paper we present a completecompositional schedulability analysis for the Multi-ResourceServer technique. Based on the proposed analysis, we further providean experimental study that investigates the behaviour of theMRS and identify the factors that contribute mostly on the overallsystem performance.

  • 10.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Support for Legacy Real-Time Applications in an HSF-Enabled FreeRTOS - a technical report2014Report (Refereed)
    Abstract [en]

    This paper presents a runtime support to consolidate legacy together with other real-time applications, running a single instance of a real-time operating system (RTOS), and sharing system resources. In this context, we resort to the hierarchical scheduling framework (HSF) to provide tem- poral partitions for dierent applications, supporting their independent development and real-time analysis, thus resulting on a predictable inte- gration. In particular, the paper focuses on a constructive element, the legacy server that allows executing code that is unaware of the temporal partition within which it is deployed. Furthermore, we discuss the chal- lenges that need to be addressed to execute a legacy application in an HSF without modications to the original code. We focus on the chal- lenge of enabling sharing system resources, both hardware and software, as typically found in most industrial software systems. We propose a novel solution based on wrappers for the required RTOS system calls. We implement our ideas in a concrete implementation on FreeRTOS OS, taking advantage of a prior HSF implementation. The validation is performed by a proof-of-concept case study that shows a successful integration of a legacy application that uses shared resources in a system that executes other applications. 

  • 11.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Worst Case Delay Analysis of a DRAM Memory Request for COTS Multicore Architectures2014Conference paper (Refereed)
    Abstract [en]

    Dynamic RAM (DRAM) is a source of memory contention and interference problems on commercial of the shelf (COTS) multicore architectures. Due to its variable access time, it can greatly influence the task's WCET and can lead to unpredictability. In this paper, we provide a worst case delay analysis for a DRAM memory request to safely bound memory contention on multicore architectures. We derive a worst-case service time for a single memory request and then combine it with the per-request memory interference that can be generated by the tasks executing on same or different cores in order to generate the delay bound.

  • 12.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Carlson, Jan
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Kuncar, Jiri
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Predictable integration and reuse of executable real-time components2014In: Journal of Systems and Software, ISSN 0164-1212, E-ISSN 1873-1228, Vol. 91, p. 147-162Article in journal (Refereed)
    Abstract [en]

    We present the concept of runnable virtual node (RVN) as a means to achieve predictable integration and reuse of executable real-time components in embedded systems. A runnable virtual node is a coarse-grained software component that provides functional and temporal isolation with respect to its environment. Its interaction with the environment is bounded both by a functional and a temporal interface, and the validity of its internal temporal behaviour is preserved when integrated with other components or when reused in a new environment. Our realization of RVN exploits the latest techniques for hierarchical scheduling to achieve temporal isolation, and the principles from component-based software-engineering to achieve functional isolation. It uses a two-level deployment process, i.e. deploying functional entities to RVNs and then deploying RVNs to physical nodes, and thus also gives development benefits with respect to composability, system integration, testing, and validation. In addition, we have implemented a server-based inter-RVN communication strategy to not only support the predictable integration and reuse properties of RVNs by keeping the communication code in a separate server, but also increasing the maintainability and flexibility to change the communication code without affecting the timing properties of RVNs. We have applied our approach to a case study, implemented in the ProCom component technology executing on top of a FreeRTOS-based hierarchical scheduling framework and present the results as a proof-of-concept.

  • 13.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Cederman, Daniel
    Department of Computing Science and Engineering, Chalmers University.
    Tsigas, Philippas
    Department of Computing Science and Engineering, Chalmers University.
    A* Algorithm for Graphics Processors2010In: THIRD SWEDISH WORKSHOP ON MULTI-CORE COMPUTING - MCC'10, Chalmers University of Technology, Sweden, 2010Conference paper (Refereed)
    Abstract [en]

    Today's computer games have thousands of agents moving at the same time in areas inhabited by a large number of obstacles. In such an environment it is important to be able to calculate multiple shortest paths concurrently in an efficient manner. The highly parallel nature of the graphics processor suits this scenario perfectly. We have implemented a graphics processor based version of the A* path finding algorithm together with three algorithmic improvements that allow it to work faster and on bigger maps. The first makes use of pre-calculated paths for commonly used paths. The second use multiple threads that work concurrently on the same path. The third improvement makes use of a scheme that hierarchically breaks down large search spaces. In the latter the algorithm first calculates the path on a high level abstraction of the map, lowering the amount of nodes that needs to be visited. This algorithmic technique makes it possible to calculate more paths concurrently on large map settings compared to what was possible using the standard A* algorithm. Experimental results comparing the efficiency of the algorithmic techniques on a NVIDIA GeForce GTX 260 with 24 multi-processors are also presented in the paper.

  • 14.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Mahmud, Nesredin
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    The Multi-Resource Server for Predictable Execution on Multi-core Platforms2014In: Real-Time Technology and Applications - Proceedings, 2014, Vol. October, p. 1-11Conference paper (Refereed)
    Abstract [en]

    In this paper we present an implementation and demonstration of the Multi-Resource Server (MRS) which enables predictable execution of real-time applications on multi-core platforms. The MRS provides temporal isolation both between tasks running on the same core, as well as, between tasks running on different cores. The latter could, without MRS, interfere with each other due to contention on a shared memory bus. We demonstrate that MRS can be used to ”encapsulate” legacy systems and to give them enough resources to fulfill their purpose. In our case study a legacy media-player is integrated with several resource-hungry tasks running at a different core. We show that without MRS the media-player starts to drop frames due to the interference from other tasks; while introduction of MRS alleviates this problem. Another part of our demonstration shows how traditional periodic real-time tasks can be kept schedulable even when tasks with high memory-demand are added to the system.

  • 15.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Mäki-Turja, Jukka
    Mälardalen University, School of Innovation, Design and Engineering.
    Carlson, Jan
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Using Temporal Isolation to Achieve Predictable Integration of Real-Time Components2010In: 22nd Euromicro Conference on Real-Time Systems (ECRTS' 10) WiP Session / [ed] Robert I. Davis, 2010, p. 17-21Conference paper (Refereed)
    Abstract [en]

    We present the concept of a virtual node as means to achieve predictable integration of software components with real-time requirements. The virtual node is based on the technology using the hierarchical scheduling framework to achieve temporal isolation between components (or sets of components). The temporal isolation means that all components deployed to a virtual node will retain their temporal properties when integrated with other components on a physical node. We present how the concept of virtual nodes is applicable to three different component technologies: ProCom, Autosar and AADL. Keywords-real-time systems; component integration

  • 16.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Mäki-Turja, Jukka
    Mälardalen University, School of Innovation, Design and Engineering.
    Carlson, Jan
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Virtual Node - To Achieve Temporal Isolation and Predictable Integration of Real-Time Components2012In: International Journal on Computing (JoC), ISSN 2010-2283, Vol. 1, no 4, p. 63-69Article in journal (Refereed)
    Abstract [en]

    We present an approach of two-level deployment process for component models used in distributed real-time embedded systems to achieve predictable integration of real-time components. Our main emphasis is on the new concept of virtual node with the use of a hierarchical scheduling technique. Virtual nodes are used as means to achieve predictable integration of software components with real-time requirements. The hierarchical scheduling framework is used to achieve temporal isolation between components (or sets of components). Our approach permits detailed analysis, e.g., with respect to timing, of virtual nodes and this analysis is also reusable with the reuse of virtual nodes. Hence virtual node preserves real-time properties across reuse and integration in different contexts.

  • 17.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Mäki-Turja, Jukka
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Ashjaei, Mohammad
    Mälardalen University, School of Innovation, Design and Engineering.
    Afshar, Sara
    Mälardalen University, School of Innovation, Design and Engineering.
    Hierarchical Scheduling Framework Implementation in FreeRTOS2011Report (Other academic)
    Abstract [en]

    This report presents the implementation of hierarchical scheduling framework HSF on an open source real-time operating system FreeRTOS to support the temporal isolation of a number of real-time components (or applications) onto a single processor. The goal is to achieve predictable integration and reusability of independently developed components or tasks. It presents the initial results of the HSF implementation by running it on an AVR 32-bit board EVK1100. It addresses the fixed-priority preemptive scheduling at both global and local scheduling levels. It describes the detailed design of HSF with the emphasis of doing minimal changes to the underlying FreeRTOS kernel and keeping its API intact. Finally it provides (and compares) the results for the performance measures of periodic and deferrable servers with respect to the overhead of the implementation. Index Terms: real-time systems; hierarchical scheduling framework; fixed-priority scheduling

  • 18.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Mäki-Turja, Jukka
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Ashjaei, Mohammad
    Mälardalen University, School of Innovation, Design and Engineering.
    Afshar, Sara
    Mälardalen University, School of Innovation, Design and Engineering.
    Support for Hierarchical Scheduling in FreeRTOS2011In: 2011 IEEE 16TH CONFERENCE ON EMERGING TECHNOLOGIES AND FACTORY AUTOMATION (ETFA) / [ed] IEEE Industrial Electronic Society, IEEE conference proceedings, 2011, p. 1-10Conference paper (Refereed)
    Abstract [en]

    This paper presents the implementation of a HierarchicalScheduling Framework (HSF) on an open sourcereal-time operating system (FreeRTOS) to support the temporalisolation between a number of applications, on a single processor.The goal is to achieve predictable integration and reusability ofindependently developed components or applications. We presentthe initial results of the HSF implementation by running it onan AVR 32-bit board EVK1100.

    The paper addresses the fixed-priority preemptive schedulingat both global and local scheduling levels. It describes the detaileddesign of HSF with the emphasis of doing minimal changes tothe underlying FreeRTOS kernel and keeping its API intact.Finally it provides (and compares) the results for the performancemeasures of idling and deferrable servers with respect to theoverhead of the implementation.

  • 19.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Mäki-Turja, Jukka
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Hard Real-time Support for Hierarchical Scheduling in FreeRTOS2011In: Proceedings of 7th annual workshop on Operating Systems Platforms for Embedded Real-Time Applications July 5th, 2011 in Porto, Portugal: in conjunction with the23rd Euromicro Conference on Real-Time SystemsPortugal, July 6-8, 201 / [ed] Thomas Gleixner, Gabriel Permer, 2011, p. 51-60Conference paper (Refereed)
    Abstract [en]

    This paper presents extensions to the previous implementationof two-level Hierarchical Scheduling Framework(HSF) for FreeRTOS. The results presented here allow the useof HSF for FreeRTOS in hard-real time applications, with thepossibility to include legacy applications and components notexplicitly developed for hard real-time or the HSF.

    Specifically, we present the implementations of (i) global andlocal resource sharing using the Hierarchical Stack ResourcePolicy and Stack Resource Policy respectively, (ii) kernel supportfor the periodic task model, and (iii) mapping of original FreeRTOSAPI to the extended FreeRTOS HSF API. We also presentevaluations of overheads and behavior for different alternativeimplementations of HSRP with overrun from experiments on theAVR 32-bit board EVK1100. In addition, real-time schedulinganalysis with models of the overheads of our implementation ispresented.

  • 20.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Mäki-Turja, Jukka
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Kunčar, Jiří
    Real-Time Component Integration using Runnable Virtual Nodes2012In: Proceedings - 38th EUROMICRO Conference on Software Engineering and Advanced Applications, SEAA 2012, 2012, p. 80-84Conference paper (Refereed)
    Abstract [en]

    We present the concept of runnable virtual nodes (RVNs) as means to achieve predictable integration and temporal error-containment of real-time software components. An RVN exploits the latest techniques for hierarchical scheduling and is intended as a coarse-grained component for single-node deployment, that provides functional and temporal isolations with respect to its environment. It uses a two-level deployment process; i.e. deploying functional entities to RVNs and then deploying RVNs to physical nodes. The two-level deployment process not only gives development benefits with respect to composability, system integration, testing, validation and certification but also leverages the hierarchical scheduling to preserve the validity of an RVN's internal temporal behaviour when integrated with other components. We have applied our approach to a simple case study, implemented in the ProCom component-technology executing on top of FreeRTOS-based hierarchical scheduling and present our initial results as a proof-of-concept.

  • 21.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Mäki-Turja, Jukka
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Kunčar, Jiří
    Run-Time Component Integration and Reuse in Cyber-Physical Systems2011Report (Other academic)
    Abstract [en]

    We present the concept of runnable virtual nodes as a means to achieve predictable integration and reuse of software components in cyber-physical systems. A runnable virtual nodeis a coarse-grained real-time component that provides functional and temporal isolation with respect to its environment.Its interaction with the environment is bounded both by a functional and a temporal interface, and the validity of itsinternal temporal behavior is preserved when integrated with other components or when reused in a new environment.Our realization of runnable virtual nodes exploits the latest techniques for hierarchical scheduling to achieve temporalisolation, and the principles from component-based software-engineering to achieve functional isolation. In the paperwe present a proof-of-concept case study, implemented in the ProCom component-technology executing on top of FreeRTOSbased hierarchical scheduling framework.

  • 22.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Combating unpredictability in multicores through the multi-resource server2014In: 19th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2014, 2014, p. Article number 7005063-Conference paper (Refereed)
    Abstract [en]

    In this paper we present challenges that hinder the predictable integration and execution of real-time applications on multicore platforms. We investigate how shared resources, like CPU, memory-bus bandwidth, caches, and memory cause unpredictability and interference. We propose to adapt the traditional server-based scheduling approach on the multicore platforms with additional resource-reservations to control the shared access to such resources and present the multi-resource server as a solution such that the execution of real-time applications becomes predictable. 

  • 23.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Implementing and Evaluating Communication- Strategies in the ProCom Component Technology2012In: Acm Sigbed Review, ISSN 1551-3688, Vol. 9, no 4, p. 1-4Article in journal (Refereed)
    Abstract [en]

    This paper presents two strategies to support communication between real-time executable Runnable Virtual Node (RVN) components in the ProCom component technology. We describe the currently implemented server-based communication strategy which uses a dedicated server for communication. We compare the server-based technique with a direct (RVN-to-RVN) communication strategy. The paper also describes how these strategies could be evaluated for real-time performance, and the real-time analysis technologies needed to perform such an evaluation.

  • 24.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Bril, Reinder J.
    Technische Universiteit Eindhoven (TU/e), Eindhoven, The Netherlands.
    Implementing Hierarchical Scheduling to support Multi-Mode System2012In: 7th IEEE International Symposium on Industrial Embedded Systems (SIES) June 20 – June 22, 2012 Karlsruhe, Germany, Conference Proceedings, Karlsruhe, Germany, 2012, p. 319-322Conference paper (Refereed)
    Abstract [en]

    Multi-mode embedded real-time systems exhibit a specific behavior for each mode and upon a mode-change request, the task-set and timing interfaces of the system need to be changed. Hierarchical Scheduling Framework (HSF) is a known technique to partition the CPU time into a number of hierarchically divided subsystems each consists of its own task set. We propose to implement a multi-mode system using a two-level HSF and provide a skeleton (framework)  for an adaptive HSFs supporting multi-modes. Upon a mode-change request, the timing interface of each subsystem is changed, thus making the hierarchical scheduling adaptive in nature. We address the main goals for the implementation and describe the initial design details of Multi-Mode Adaptive Hierarchical Scheduling Framework (MMAHSF) with the emphasis of doing minimal changes to the underlying kernel.

  • 25.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    J. Bril, Reinder
    TU/e, The Netherlands.
    Mode-Change Mechanisms support for Hierarchical FreeRTOS Implementation2013Conference paper (Refereed)
    Abstract [en]

    Multi-mode embedded real-time systems exhibit a specific behaviour for each mode, and upon a mode-change request the task-set and timing interfaces of the system need to be changed. This paper presents the implementation of a Multi- Mode Adaptive Hierarchical Scheduling Framework (MMAHSF) and provides a generic skeleton (framework) for a two-level adaptive hierarchical scheduling supporting multiple modes and multiple mode-change mechanisms on an open source real-time operating system (FreeRTOS). The MMAHSF enable applicationspecific implementations of mode-change protocols using a set of predefined mode-change mechanisms. The paper addresses different mode-change mechanisms at both global and local scheduling levels. It presents examples of mode-change protocols that are developed by composing together these mechanisms in multiple ways and provide the initial results of executing these protocols in the MMAHSF implementation on an AVR 32-bit board EVK1100.

  • 26.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Marcus, Jägemar
    Mälardalen University, School of Innovation, Design and Engineering. Ericsson AB.
    Bandwidth Measurement using Performance Counters for Predictable Multicore Software2012In: IEEE Symposium on Emerging Technologies and Factory Automation, ETFA 2012, 2012, , p. 4p. Article number: 6489714-Conference paper (Other (popular science, discussion, etc.))
    Abstract [en]

    Memory contention is one of the largest sources of inter-core interference in statically partitioned multicore systems, and the contention reduces the overall performance of applications and causes unpredictable execution-times. A first step in achieving predictable execution is to accurately measure the amount of consumed memory bandwidth for each application. Such measurements can be used to track down bottlenecks, provide better partitioning among cores, and ultimately be used to arbitrate and police access to the memory bus. We propose to use hardware performance counters to continuously track the memory-bandwidth consumed by different applications executing in parallel. In this paper we describe ongoing efforts exploring suitable performance counters on core-level and on system-on-chip level for the 8-core Freescale P4080 processor. The aim is to accurately and efficiently track consumed memory bandwidth per application; with the final goal to use these measurements to improve predictability of multicore real-time software.

  • 27.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Slatman, Joris
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Towards Implementing Multi-resource Server on Multi-core Linux Platform2013In: Proceedings of 18th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA2013), 2013, p. Article number 6648167-Conference paper (Refereed)
    Abstract [en]

    In this paper we present our ongoing work on implementing the multi-resource server technology in the Linux operating system running on multi-core architectures. The multiresource server is used to control the access to both CPU and memory bandwidth resources such that the execution of real-time tasks become predictable. We are targeting Legacy applications to be migrated from single to multi-core architectures. We investigate the available techniques and mechanisms that can support our multi-resource servers and we discuss the potential problems that needed to be tackled considering the requirements of legacy applications.

  • 28.
    Kunčar, Jiří
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Inam, Rafia
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    End-to-End Latency Analyzer for ProCom - EELAP2013Report (Other academic)
    Abstract [en]

    This report presents an analysis tool End-to-End Latency Analyzer for ProCom (EELAP) developed to compute different end-to-end latency semantics for multi-rate components of real-time embedded systems. ProCom component technology implements executable reusable real-time components called Runnalbe Virtual Nodes (RVNs) and supports two different communication strategies for inter-RVN communication. The tool is developed to evaluate the two communication strategies for multi-rate server-based components the ProCom component technology. In this report we present a user guide for EELAP. We describe the formulas and corresponding algorithms used to compute end-to-end latency semantics, and response-times of the tasks executing in a two-level hierarchical scheduling framework. Further, we provide a detailed description of APIs.

  • 29.
    Nemati, Farhang
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Inam, Rafia
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Towards Resource Sharing by Message Passing among Real-Time Components on Multi-cores2011In: 2011 IEEE 16th International Conference on Emerging Technology and Factory Automation, ETFA 2011,Toulouse, France; 5 September 2011 through 9 September 2011, Toulouse, France, 2011, p. 1-4Conference paper (Refereed)
  • 30.
    Yin, Hang
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Inam, Rafia
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, Reinder J.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Formalization and verification of mode changes in hierarchical scheduling2014Conference paper (Refereed)
    Abstract [en]

    Hierarchical scheduling frameworks (HSFs) are a means for composing complex real-time embedded systems from independently developed and analyzed applications. To support multiple modes in a two-level HSF, the multi-mode adaptive hierarchical scheduling framework MMAHSF has recently been presented supporting different mode-change mechanisms. Currently, we provide a formalization and verification of mode changes in MMAHSF using the UPPAAL model checker for certain mode-change mechanisms. The verification indicates that MMAHSF and the proposed mode-change mechanisms are deadlock-free and guarantee mode changes in bounded time.

  • 31.
    Yin, Hang
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Inam, Rafia
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, Reinder J.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Formalization and verification of mode changes in hierarchical scheduling---An extended report2014Report (Other academic)
    Abstract [en]

    Hierarchical scheduling frameworks (HSFs) are a means for composing complex real-time embedded systems from independently developed and analyzed applications. To support multiple modes in a two-level HSF, the multi-mode adaptive hierarchical scheduling framework MMAHSF has recently been presented supporting different mode-change mechanisms. Currently, we provide a formalization and verification of mode changes in MMAHSF using the UPPAAL model checker for certain mode-change mechanisms. The verification indicates that MMAHSF and the proposed mode-change mechanisms are deadlock-free and guarantee correct mode changes in bounded time.

1 - 31 of 31
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf