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  • 1.
    Ciccozzi, Federico
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Cicchetti, Antonio
    Mälardalen University, School of Innovation, Design and Engineering.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Åkerberg, Johan
    Mälardalen University, School of Innovation, Design and Engineering.
    Delsing, Jerker
    Mälardalen University, School of Innovation, Design and Engineering.
    Carlsson, Lars Eric
    Mälardalen University, School of Innovation, Design and Engineering.
    Integrating Wireless Systems into Process Industry and Business Management2010In: ETFA10 - IEEE International Conference on Emerging Technology and Factory Automation, Bilbao, Spain, 2010Conference paper (Refereed)
    Abstract [en]

    We analyze here the topic of integration, in the area of process automation, from sensor/actuator levels to plant management levels. The communication at fieldbus level is based on wireless technology while management applications run in wired control systems, but can also be distributed, communicating via the Internet. This work aims at building a real-life demonstrator at Boliden, a mining and smelting plant located in Boliden, Sweden.. A small process control environment is to be deployed at the plant to supervise a tank level control system. Targeted results are an interface between wireless and wired systems, the deployment of a wireless process control environment at Boliden, and the development of the enterprise business management facilities.

  • 2.
    Ciccozzi, Federico
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Corcoran, Diarmuid
    Ericsson AB, Kista, Sweden.
    Seceleanu, Tiberiu
    ABB Corporate Research, Vasteras, Sweden.
    Scholle, Detlef
    Alten Sverige AB, Sweden.
    SMARTCore: Boosting Model-Driven Engineering of Embedded Systems for Multicore2015In: Proceedings - 12th International Conference on Information Technology: New Generations, ITNG 2015, 2015, Vol. Article number 7113454, p. 89-94Conference paper (Refereed)
    Abstract [en]

    Thanks to continuous advances in both software and hardware technologies the power of modern embedded systems is ever increasing along with their complexity. Among the others, Model-Driven Engineering has grown consideration for mitigating this complexity through its ability to shift the focus of the development from hand-written code to models from which correct-by-construction implementation is automatically generated. However, the path towards correctness-by-construction is often twisted by the inability of current MDE approaches to preserve certain extra-functional properties such as CPU and memory usage, execution time and power consumption. With SMARTCore we address open challenges, described in this paper together with an overview of possible solutions, in modelling, generating code from models, and exploiting back-propagated extra-functional properties observed at runtime for deployment optimisation of embedded systems on multicore. SMARTCore brings together world leading competence in software engineering, model-driven engineering for embedded systems (Mälardalen University), and market leading expertise in the development of these systems in different business areas (ABB Corporate Research, Ericsson AB, Alten Sweden AB).

  • 3.
    Ciccozzi, Federico
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Corcoran, Diarmuid
    Ericsson Software Research.
    Scholle, Detlef
    Alten Sverige AB.
    UML-based Development of Embedded Real-Time Software on Multi-core in Practice: Lessons Learned and Future Perspectives2016In: IEEE Access, E-ISSN 2169-3536, E-ISSN 2169-3536, Vol. 4Article in journal (Refereed)
    Abstract [en]

    Model-Driven Engineering has got a foothold in industry as an effective way to tame the complexity of modern software which is meant to run on embedded systems with real-time constraints by promoting abstraction, in terms of prescriptive models, and automation, in terms of model manipulations. In the plethora of modelling languages, the Unified Modeling Language (UML) has emerged and established itself as a de facto standard in industry, the most widely used architectural description language and an ISO/IEC standard. In the SMARTCore project we have provided solutions for UML-based development of software to run on multicore embedded real-time systems with the specific focus of automating the generation of executable code and the optimization of task allocation based on a unique combination of model-based and execution-based mechanisms. In this paper we describe the lessons learned in the research work carried out within SMARTCore and provide a set of perspectives that we consider to be highly relevant for the forthcoming future of this research area to enable a wider adoption of UML-based development in industry in general, and in the multicore embedded real-time domain in particular.

  • 4.
    Danielsson, Jakob
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Marcus, Jägemar
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Ericsson AB, Stockholm, Sweden.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Measurement-based evaluation of data-parallelism for OpenCV feature-detection algorithms2018In: Staying Smarter in a Smartening World COMPSAC'18, 2018, p. 701-710Conference paper (Refereed)
    Abstract [en]

    We investigate the effects on the execution time, shared cache usage and speed-up gains when using data-partitioned parallelism for the feature detection algorithms available in the OpenCV library. We use a data set of three different images which are scaled to six different sizes to exercise the different cache memories of our test architectures. Our measurements reveal that the algorithms using the default settings of OpenCV behave very differently when using data-partitioned parallelism. Our investigation shows that the executions of the algorithms SURF, Dense and MSER correlate to L3-cache usage and they are therefore not suitable for data-partitioned parallelism on multi-core CPUs. Other algorithms: BRISK, FAST, ORB, HARRIS, GFTT, SimpleBlob and SIFT, do not correlate to L3-cache in the same extent, and they are therefore more suitable for data-partitioned parallelism. Furthermore, the SIFT algorithm provides the most stable speed-up, resulting in an execution between 3 and 3.5 times faster than the original execution time for all image sizes. We also have evaluated the hardware resource usage by measuring the algorithm execution time simultaneously with the L3-cache usage. We have used our measurements to conclude which algorithms are suitable for parallelization on hardware with shared resources.

  • 5.
    Feljan, Juraj
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Carlson, Jan
    Mälardalen University, School of Innovation, Design and Engineering.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Towards a model-based approach for allocating tasks to multicore processors2012In: Proceedings - 38th EUROMICRO Conference on Software Engineering and Advanced Applications, SEAA 2012, 2012, p. 117-124Conference paper (Refereed)
    Abstract [en]

    Multicore technology provides a way to improve the performance of embedded systems in response to the demand in many domains for more and more complex functionality. However, increasing the number of processing units also introduces the problem of deciding which task to execute on which core in order to best utilize the platform. In this paper we present a model-based approach for automatic allocation of software tasks to the cores of a soft real-time embedded system, based on design-time performance predictions. We describe a general iterative method for finding an allocation that maximizes key performance aspects while satisfying given allocation constraints, and present an instance of this method, focusing on the particular performance aspects of timeliness and balanced computational load over time and over the cores.

  • 6.
    Gaetana, Sapienza
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Goran, Brestovac
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Robi, Grgurina
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Tiberiu, Seceleanu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    On applying multiple criteria decision analysis in embedded systems design2016In: Design automation for embedded systems, ISSN 0929-5585, E-ISSN 1572-8080, Vol. 20, p. 211-238Article in journal (Refereed)
    Abstract [en]

    We focus here on the application of multi critera decision analysis (MCDA) techniques in hardware/software partitioning activities to be used in the design and deployment of embedded systems. Our goal is to identify the best existing methods and tools suitable to support the approach we have taken for the partitioning process. We provide this via a survey of the most well-known MCDA methods and tools (for a specific class of MCDA methods called multi attribute decision making. We identify a set of criteria that need to be addressed, in some way, by the methods, and implemented by related tools. These "11-suitability criteria" help us in deciding the appropriateness of the analysed methods and tools for the envisaged partitioning approach. In brief, we are interested that the MCDA methods are taking into account multiple extra-functional properties, expressed by a variety of types, with possible missing values, should enable dependency handling, decision traceability, etc. The conclusion is that there are criteria that are not fulfilled by any of the methods, and hence there is no method or tool that can directly used for the partitioning. However, the results shows the potential of using MCDA in the partitioning process and provide a good starting point for future research activities.

  • 7.
    Gaetana, Sapienza
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research, Västerås, Sweden.
    Sentilles, Séverine
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research, Västerås, Sweden.
    Crnkovic, Ivica
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Chalmers, Gothenburg, Sweden.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research, Västerås, Sweden.
    Extra-Functional Properties Composability for Embedded Systems Partitioning2016In: Proceedings - 2016 19th International ACM SIGSOFT Symposium on Component-Based Software Engineering, CBSE 2016, 2016, p. 69-78Conference paper (Refereed)
    Abstract [en]

    Modern embedded systems utilize the advances in heterogeneous platforms that enable implementing functions in software (SW) and hardware (HW) components. A proper configuration of SW and HW components can significantly improve the values of the extra-functional properties such as performance and energy savings. However, due to increasing application complexity, it is difficult to find the best combination of HW and SW components. The problem basically boils down to calculate, for a given architecture, the system properties from the components' ones. In this paper, we address the problem of composability of EFPs at system level. Although in general this is not a solvable problem, we present that, under strictly specified constraints, it is possible to compose the system EFPs starting from the component ones. We start by detailing constraints related to the system architecture, platform and process development and, based on these constraints, we provide composition rules for different types of EFPs. We demonstrate the results through an industrial example.

  • 8.
    Latif, K.
    et al.
    University of Turku.
    Rahmani, A. -M
    University of Turku.
    Nigussie, E.
    University of Turku.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Radetzki, M.
    University of Stuttgart.
    Tenhunen, H.
    University of Turku.
    Partial virtual channel sharing: A generic methodology to enhance resource management and fault tolerance in networks-on-chip2013In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 29, no 3, p. 431-452Article in journal (Refereed)
    Abstract [en]

    We present a novel Partial Virtual channel Sharing (PVS) NoC architecture which reduces the impact of faults on performance and also tolerates faults within the routing logic. Without PVS, failure of a component impairs the fault-free connected components, which leads to considerable performance degradation. Improving resource utilization is key in enhancing or sustaining performance with minimal overhead when faults or overload occurs. In the proposed architecture, autonomic virtual-channel buffer sharing is implemented with a novel algorithm that determines the sharing of buffers among a set of ports. The runtime allocation of the buffers depends on incoming load and fault occurrence. In addition, we propose an efficient technique for maintaining the accessibility of a processing element (PE) to the network even if its router is faulty. Our techniques can be used in any NoC topology and for both, 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate 22 % reduction in average packet latency compared to state-of-the-art virtual channel (VC) based NoC architecture. Extensive quantitative simulation has been carried out with synthetic benchmarks. Simulation results reveal that the PVS architecture improves the performance significantly in presence of faults, compared to other VC-based NoC architectures. 

  • 9.
    Latif, K.
    et al.
    University of Turku.
    Rahmani, A. -M
    University of Turku.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Tenhunen, H.
    University of Turku.
    Designing a high performance and reliable networks-on-chip using network interface assisted routing strategy2012In: 2012 15th Euromicro Conference on Digital System Design (DSD): proceeding, 2012, p. 34-41Conference paper (Refereed)
    Abstract [en]

    Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, we present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5X6 crossbar is used for the proposed architecture which requires one more 5X1 multiplexer without increasing the critical path delay of the router as compared to the 5X5 crossbar. The proposed router has been simulated for uniform and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead. © 2012 IEEE.

  • 10.
    Latif, Khalid
    et al.
    University of Turku, Finland.
    Rahmani, Amir-Mohammad
    University of Turku, Finland.
    Guang, Liang
    Mälardalen University, School of Innovation, Design and Engineering. University of Turku, Finland.
    Seceleanu, Tiberiu
    ABB Corporate Research, Västerås, Sweden .
    Tenhunen, Hannu
    University of Turku, Finland.
    PVS-NoC: Partial Virtual Channel Sharing NoC Architecture2011In: Proceedings - 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011, 2011, p. 470-477Conference paper (Refereed)
    Abstract [en]

    A novel architecture aiming for ideal performance and overhead tradeoff, PVS-NoC (Partial VC Sharing NoC), is presented. Virtual channel (VC) is an efficient technique to improve network performance, while suffering from large silicon and power overhead. We propose sharing the VC buffers among dual inputs, which provides the performance advantage as conventional VC-based router with minimized overhead. We reason theoretically and demonstrate quantitatively the benefits of proposed architecture by comparing to state-of-the-art NoC routers, with various traffic patterns. Extensive experiments with synthetic and real benchmarks show significant area and power saving with similar performance compared to latest VC based NoC architectures.

  • 11.
    Latif, Khalid
    et al.
    University of Turku, Finland .
    Rahmani, Amir-Mohammad
    University of Turku, Finland .
    Nigussie, Ethiopia
    University of Turku, Finland .
    Seceleanu, Tiberiu
    ABB Corporate Research, Västerås.
    Liljeberg, P
    University of Turku, Finland .
    Tenhunen, Hannu
    Mälardalen University, School of Innovation, Design and Engineering. University of Turku, Finland .
    Enhancing Performance Sustainability of Fault Tolerant Routing Algorithms in NoC-Based Architectures2011In: Proceedings - 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, 2011, p. 626-633Conference paper (Refereed)
    Abstract [en]

    Reliability of embedded systems and devices is becoming a challenge with technology scaling. To deal with the reliability issues, fault tolerantsolutions are needed. The design paradigm for future System-on-Chip (SoC) implementation is Network-on-Chip (NoC). Fault tolerance in NoC can be achieved at many abstraction levels. Many fault tolerant architectures and routing algorithms have already been proposed for NoC but the utilization of resources, affected indirectly by faults is yet to be addressed. In this paper, we propose a NoC architecture, which sustains the overall systemperformance by utilizing resources, which cannot be used by other architectures under faults. An approach towards a proper virtual-channel (VC) sharing strategy is proposed, based on communication bandwidth requirements. The technique can be applied to any NoC architecture, including 3-D NoCs. Extensive quantitative experiments with synthetic benchmarks, including uniform, transpose and negative exponential distribution (NED), demonstrate considerable improvement in terms of performance sustainability under faulty conditions compared to existing VC-based NoCarchitectures.

  • 12.
    Latif, Khalid
    et al.
    University of Turku, Finland .
    Rahmani, Amir-Mohammad
    University of Turku, Finland .
    Nigussie, Ethiopia
    University of Turku, Finland .
    Tenhunen, Hannu
    University of Turku, Finland .
    Seceleanu, Tiberiu
    ABB Corporate Research, Västerås.
    A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip2011In: Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2011, p. 452-462Conference paper (Refereed)
    Abstract [en]

    We present the partial virtual-channel sharing (PVS) NoC architecture which reduces the impact of fault on system performance and can also tolerate the faults on routing logic. A fault in one component makes the fault-free connected components out of use and this in turn leads to considerable performance degradation. Improving utilization of resources is a key to either enhance or sustain performance with minimal overheads in case of fault or overloading. In the proposed architecture autonomic virtual-channel buffer sharing is implemented. The runtime allocation of the buffers depends on incoming load and fault occurrence. This technique can be used in any NoC topology and for both 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate significant reduction in average packet latency compared to existing VC-based NoC architecture. Extensive quantitative simulation results for synthetic benchmarks are also carried out. Furthermore, the simulation results reveal that the PVS architecture improves the performance significantly under fault free conditions compared to other VC architectures.

  • 13.
    Latif, Khalid
    et al.
    University of Turku.
    Rahmani, Amir-Mohammad
    University of Turku.
    Seceleanu, Tiberiu
    ABB.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    A Low-Cost Processing Element Recovery Mechanism for Fault Tolerant Networks-on-Chip2011In: 2011 NORCHIP, United States, 2011, Vol. 17, no 1Conference paper (Refereed)
    Abstract [en]

    A fault in one component of Networks-on-Chip (NoC) based system makes the fault-free connected units out of use and this in turn leads to considerable performance degradation. Many fault tolerant architectures and routing algorithms have already been proposed for NoC but the utilization of resources, affected indirectly by faults is yet to be addressed. It is indispensable step needed to be taken in order to implement the reliable on-chip systems especially with nano-scale technologies. In this paper, we present a technique to recover healthy processing elements for NoC architectures in case of associated routers failure by using the Partial Virtual-Channel Sharing (PVS) approach. The proposed architecture divides the network into cluster regions, where each cluster comprises of two nodes. Each node in a cluster provides a backup data-path for other node in the cluster. Each processing element can use the backup data-path to transmit and receive the packets in case of corresponding router failure. The simulation results show that the proposed architecture has low hardware overheads.

  • 14.
    Latif, Khalid
    et al.
    University of Turku.
    Rahmani, Amir-Mohammad
    University of Turku.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    An Autonomic NoC Architecture using Heuristic Technique for Virtual Channel Sharing2011In: Autonomic Networking-on-Chip: Bio-Inspired Specification, Development, and Verification / [ed] Phan Cong-Vinh, CRC Press , 2011, p. 48-68Chapter in book (Other academic)
  • 15.
    Latif, Khalid
    et al.
    University of Turku.
    Rahmani, Amir-Mohammad
    University of Turku.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    Power- and Performance-Aware IP Mapping for NoC-Based MPSoC Platforms2010In: / [ed] IEEE, 2010, p. 760-763Conference paper (Refereed)
    Abstract [en]

    In this paper, we address the performance of MPSoC platforms with homogeneous processing nodes, where the cores generate and consume the large amount of data, thus the system approaches congestion. Mostly, the time dependent media applications are time critical, where traffic must be delivered on time in order to operate properly. Proper task allocation or placement of IP cores at layout time is very important to meet such application requirements. Apart from meeting the application requirements, it also lowers the traffic congestion, power consumption and Average Packet Latency (APL). For task allocation or IP placement, the prioritization criteria has been proposed, which is used in next step to map the application on MPSoC platform. The proposed technique shows significant improvement in system performance and reduction in power consumption. To estimate the efficiency, the video conference encoding application and MPEG4 video encoder were mapped to 5x5 and 4x4 NoC mesh. Up to 11% reduction in power consumption and 20% reduction in APL has been observed as compared to other proposed mapping techniques.

  • 16.
    Latif, Khalid
    et al.
    University of Turku.
    Rahmani, Amir-Mohammad
    University of Turku.
    Seceleanu, Tiberiu
    ABB Corporate Research, Sweden.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    Liljeberg, Pasi
    University of Turku, Finland.
    Enhancing Performance of NoC-Based Architectures using Heuristic Virtual-Channel Sharing Approach.2011Conference paper (Refereed)
    Abstract [en]

    This paper presents a novel virtual-channel (VC)sharing technique for NoC architecture. The proposed architectureimproves the utilization of resources to enhance theperformance with minimal overheads. A heuristic approachtowards the proper VC sharing strategy is proposed, which isperformed by an adaptive algorithm that configures the VCsharing based on link load parameters. Architectural designto realize the adaptive VC sharing in generic router is elaborated.The technique can be applied to any NoC architecture,including 3-D NoCs. Extensive quantitative experiments withsynthetic and real benchmarks, including an integrated videoconference application, demonstrate considerable improvementin area and power efficiency compared to existing VC-based2D/3D NoC architectures.

  • 17.
    Latif, Khalid
    et al.
    University of Turku.
    Rahmani, Amir-Mohammad
    University of Turku.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    Seceleanu, Tiberiu
    ABB Corporate Research, Västeras, Sweden .
    A Cluster-Based Core Protection Technique for Networks-on-Chip2012In: Proceedings - International Computer Software and Applications Conference 2012, 2012, p. 360-361Conference paper (Refereed)
    Abstract [en]

    Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, a cluster based processing core protection technique for NoC systems using PVS approach is presented. In case of network level faults, the processing core of faulty node can use any other router in the cluster for transmission or reception of data packets with proposed architecture. Simulation results show significant reduction in average packet latency at the expense of negligible area overhead.

  • 18.
    Latif, Khalid
    et al.
    University of Turku.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Seceleanu, Cristina
    Mälardalen University, School of Innovation, Design and Engineering.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    Resource-Aware Task Allocation and Scheduling for SegBus Platform2010In: 2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings, 2010, p. 523-526Conference paper (Refereed)
    Abstract [en]

    In this work, we propose an integrated task allocation and scheduling mechanism to minimize the resource contention and the processing latency for application running on the SegBus platform. The transactions are classified as local and cross border SPLIT transactions. The hybrid scheduling approach implemented by hierarchal arbiter code structure shows significant improvement in system performance. The interrupt scheduling has been implemented to further enhance system performance. A H.264 video encoder application has been used to verify the proposed technique, showing a large improvement in system throughput.

  • 19.
    Latif, Khalid
    et al.
    Univ Turku, Finland.
    Seceleanu, Tiberiu
    ABB Corp Res, Västerås.
    Seceleanu, Cristina
    Mälardalen University, School of Innovation, Design and Engineering.
    Tenhunen, Hannu
    Univ Turku, Finland.
    Service based communication for MPSoC platform-SegBus2011In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 35, no 7, p. 643-655Article in journal (Refereed)
    Abstract [en]

    MPSoC platforms offer solutions to deal with communication limitations for multiple cores on single chip, but many new issues arise within the context. The SegBus platform is one of the solutions for application deployment on multi-core applications. There are many applications where identical data is transferred from the same source towards different destinations. Multicast services may come as a performance improving factor for the interconnection platform, together with interrupt service. In this paper, the task is to analyze, how different services can be designed for the SegBus platform and observe the improvement in system performance. The designer can select the services according to the requirements. The running example is represented by the H.264 encoder. The SegBus platform architecture, the communication mechanism, the allocation of processing elements on the platform, the communication services and their implementation are the main topics elaborated here.

  • 20.
    Latif, Khalid
    et al.
    University of Turku.
    Seceleanu, Tiberiu
    ABB Corporate Research, Västerås.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    Application Specific IP Placement for On-Chip Distributed Architectures2009In: 2009 NORCHIP, 2009Conference paper (Refereed)
    Abstract [en]

    In this paper we approach the performance aspects of MPSoC platforms, from the point of view of IP placement with the focus onNetwork-on-Chip(NoC). Proper IP placement is important for several time-dependent applications such as video and voice where traffic must be delivered on time in order to operate properly. Proper placement of IPs can lower the traffic congestion, improve overall execution time and power consumption. We have suggested a new criteria for the prioritization of IPs regarding placement. Based onthat criteria, we implemented an algorithm for IP placement.The running example is represented by mapping of H.264 encoderapplication on a NoC mesh. Allocation of processing elements on the platform, topology and communication mechanism are the main topics described here.

  • 21.
    Latif, Khalid
    et al.
    University of Turku.
    Seceleanu, Tiberiu
    ABB Corporate Research, Sweden.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    MultiCast Protocol for SegBus Platform.2009In: 2009 NORCHIP, 2009, p. 33-38Conference paper (Refereed)
    Abstract [en]

    The task is to analyze, how different services can be designed for the SegBus multiprocessor platformand observe the improvement in system performance. In this paper, we utilize the concept of broadcasting and multicasting service from standard data bus for multiprocessor systems to enhance the performance of SegBus platform. The running example is represented by the H.264 encoder. TheSegBus platform architecture, the communication mechanism, the arbitration scheme, the allocation of processing elements on the platform, and the broadcasting services and their implementation are the main topics analyzed here.

  • 22.
    Latif, Khalid
    et al.
    University of Turku.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers2010In: / [ed] IEEE, 2010, p. 131-138Conference paper (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to reduce the chip area and power consumption. Virtual channel buffer sharing by other router ports has been proposed to enhance the performance of on-chip communication. We approach the router architecture optimization by utilizing the idle buffers instead of increasing the number and size of buffers for desired throughput.

  • 23.
    Lednicki, L.
    et al.
    ABB Corporate Research, Sweden.
    Sapienza, Gaetana
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research, Sweden.
    Johansson, M. E.
    ABB Corporate Research, Sweden.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research, Sweden.
    Hallmans, D.
    ABB Power Systems HVDC, Sweden.
    Integrating Version Control in a Standardized Service-Oriented Tool Chain2016In: Proceedings - International Computer Software and Applications Conference, 2016, p. 323-328Conference paper (Refereed)
    Abstract [en]

    The complexity of modern embedded systems most often requires multiple specialized tools to be used during the development process. These tools are commonly integrated into tool chains. An efficient way of achieving such integration is through the use of an tool integration framework, with one of the most prominent of such frameworks being Open Services for Lifecycle Collaboration (OSLC). However, at present time OSLC does not provide an established way for fully integrating version control systems. This paper presents how version control systems can be integrated into a tool chain based on OSLC. The integration is enabled by defining a version control domain based on the OSLC core specification, describing how to represent versioned artifacts and perform version control operations. The proposed approach is implemented and its feasibility is proven on a case study tool chain, which integrates the Team Foundation Server version control system and an industrial design tool for the power distribution domain.

  • 24.
    Niazi, M. F.
    et al.
    Turku Centre for Computer Science, Turku, Finland .
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Tenhunen, H.
    Turku Centre for Computer Science, Turku, Finland .
    A development and verification framework for the SegBus platform2013In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 59, no 10 PART C, p. 1015-1031Article in journal (Refereed)
    Abstract [en]

    We describe the creation of a development framework for a platform-based design approach, in the context of the SegBus platform. The work intends to provide automated procedures for platform build-up and application mapping. The solution is based on a model-based process and heavily employs the UML. We develop a Domain Specific Language to support the platform modeling. An emulator is consequently introduced to allow an as much as possible accurate performance estimation of the solution, at high abstraction levels. Automated execution schedule generation is also featured. The resulting framework is applied to build actual design solutions for a MP3-decoder application. 

  • 25.
    Niazi, Moazzam
    et al.
    University of Turku.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    A Performance Estimation Technique for the SegBus Distributed Architecture2010In: / [ed] IEEE, 2010, p. 89-98Conference paper (Refereed)
    Abstract [en]

    We propose a performance estimation technique for a multi-core segmented bus platform, SegBus. The technique enables us to assess the performance aspects of any specific application on a particular platform configuration, modeled in Unified Modeling Language (UML). We present methods to transform Packet Synchronous Data Flow (PSDF) and Platform Specific Model (PSM) models of the application into Extensible Markup Language (XML) schemes using modeling tool and how the generated XML schemes can be utilized by the emulator program to get the execution results. The technique facilitates us to estimate performance aspects of application mapped on a number of different platform configurations during the early stages of the design process.

  • 26.
    Niazi, Moazzam
    et al.
    University of Turku.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    An Automated Control Code Generation Approach for the SegBus Platform2010In: / [ed] IEEE, 2010, p. 199-204Conference paper (Refereed)
  • 27.
    Niazi, Moazzam
    et al.
    University of Turku.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Tenhunen, Hannu
    Turku Centre for Computer Science.
    Towards Reuse-based Development for the On-Chip Distributed SoC Architecture2013In: Proceedings - International Computer Software and Applications Conference, 2013, p. 278-283Conference paper (Refereed)
    Abstract [en]

    The development of a reusable library of components for a multi-core segmented bus platform, the SegBus, is presented. The library is based on a plug-in that we develop and deploy within a modeling tool which eventually used by the SegBus DSL while developing applications targeting the SegBus platform. The steps required in building the library and embed it into a plug-in are discussed together with the certain use of it in our design methodology.

  • 28.
    Nita, Iulian
    et al.
    Polytechnica University Bucharest, Romania.
    Costachioiu, T
    Polytechnica University Bucharest, Romania.
    Lazarescu, V
    Polytechnica University Bucharest, Romania.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Multiprocessor real time edge detection using FPGA IP cores2011In: Proceedings - 2011 IEEE 7th International Conference on Intelligent Computer Communication and Processing, ICCP 2011, 2011, p. 331-334Conference paper (Refereed)
    Abstract [en]

    Real time edge detection is required in many embedded systems where execution speed is critical. This task is intensely computational but highly parallelizable and, in order to satisfy the real-time requirements, using multiprocessor-based embedded systems can be a viable solution. In this paper we propose a MPSoC hardware and software co-design method for real-time Sobel edge detection using FPGA and IP blocks. The experiments we performed show a speed-up of 1.71 in the case of a multiprocessor system with two processors and a speed-up of 3.48 in the case of a multiprocessor system with four processing cores, versus a single processor system

  • 29.
    Nita, Iulian
    et al.
    Polytechnica University Bucharest, Romania.
    Rapan, Adrian
    Polytechnica University Bucharest, Romania.
    Lazarescu, Vasile
    Polytechnica University Bucharest, Romania.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Efficient threads mapping on multicore architecture2010In: / [ed] IEEE, 2010, p. 53-56Conference paper (Refereed)
    Abstract [en]

    Considering today's hardware performance, in order to obtain best results, a proper programming strategy for optimum mapping of all processes to existing resources is necessary. The presence of multiple cores in a single chip requires applications with a higher level of parallelism. The use of suited mapping algorithms can lead to a great performance improvement considering computing time at a smaller energy consumption. We've realized a comparison between the parallel computing with an efficient mapping algorithm of threads to specific cores and parallel computing with threads mapping maintained by Linux kernel process scheduler. We observed that a good strategy regarding thread mapping on different processing units, balancing all available cores and allocating a specific amount of work, can lead to improved computational time. In our simulation we used Kubuntu Linux operating system, a system with Intel Core 2 Duo processor and another system with an Intel Quad Core.

  • 30. Salimi, Maghsood
    et al.
    Majd, Amin
    Loni, Mohammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Seceleanu, Cristina
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sirjani, Marjan
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Troubitsyna, Elena
    Multi-objective Optimization of Real-Time Task Scheduling Problem for Distributed Environments2019In: 6th Conference on the Engineering of Computer Based Systems ECBS 2019, 2019Conference paper (Refereed)
  • 31.
    Sapienza, Gaetana
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Brestovac, Goran
    Grgurina, Robi
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Assessing Multiple Criteria Decision Analysis Suitability for HW/SW Deployment in Embedded Systems DesignIn: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165Article in journal (Refereed)
  • 32.
    Sapienza, Gaetana
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Crnkovic, Ivica
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Modelling for Hardware and Software Partitioning based on Multiple Properties2013In: Proceedings - 39th Euromicro Conference Series on Software Engineering and Advanced Applications, SEAA 2013, 2013, p. 189-194Conference paper (Refereed)
    Abstract [en]

    In many embedded systems types the separation process for deploying the applications as software and hardware executable units, called partitioning is crucial. This is due to the fact that partitioning decisions impact the overall life cycle of the systems. In industry it is common practice to take partitioning decisions in an early stage of the design, based on hardware and software designers expertise. We propose a new methodology as a combination of modelbased and component-based approaches which enables a late partitioning decisions based on high level system requirements and project constrains. The final partitioning is decided based on a multi-property analysis approach. Here, we focus on the formalization of the overall process and in particular on the definition of a comprehensive system metamodel. This is meant to support modelling approaches suitable for enabling both the partitioning and reuse. An industrial case study is used to illustrate the approach.

  • 33.
    Sapienza, Gaetana
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Crnkovic, Ivica
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Technical Report: Modelling for hardware and software deployment based on multiple properties selection2013Report (Other academic)
    Abstract [en]

    This technical report is an appendix to a paper Gaetana Sapienza, Ivica Crnkovic, Tiberiu Seceleanu, Modelling for hardware and software deployment based on multiple properties selection, 2012 The report contains (1) a full specification of a embedded component-based system model using in MultiPart approach, and (2) a full specification of the Wind Turbine controller model generated by Simulink.

  • 34.
    Sapienza, Gaetana
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Crnkovic, Ivica
    Mälardalen University, School of Innovation, Design and Engineering.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Towards a Methodology for Hardware and Software Design Separation in Embedded Systems2012In: Proceedings of the Seventh International Conference on Software Engineering Advances (ICSEA 2012), 2012, p. 557-562Conference paper (Refereed)
    Abstract [en]

    Development of embedded systems in automation industry often includes development of both software and hardware, which requires both software and hardware expertise. In the current practice these expertise are not often completely combined in synergic ways. Traditionally, design gets separated into hardware design and software design at very early stage which negatively impacts the overall application development process due to design flow interruption and redesign. In order to overcome to the aforementioned problems, this paper presents a new design methodology that provides platform independent design first, and pushes hardware- and software-dependent design to a later stage. This enables “software-independent” hardware and “hardware-independent” software development after the separation stage, which collectively improve the overall development process.

  • 35.
    Sapienza, Gaetana
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. IS (Embedded Systems).
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    High-level design of an orchestrator for embedded systems tools2016Report (Other academic)
  • 36.
    Sapienza, Gaetana
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Crnkovic, Ivica
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Partitioning decision process for embedded hardware and software deployment2013In: Proc Int Comput Software Appl Conf, 2013, p. 674-680Conference paper (Refereed)
    Abstract [en]

    Many types of embedded systems applications are implemented as a combination of software and hardware. For such systems the mapping of the application units into hardware and software, i.e. The partitioning process, is a key phase of the design. Although there exist techniques for partitioning, the entire process, in particular in relation to different application requirements and project constraints, is not properly supported. This leads to several unplanned iterations, redesigns and interruptions due to uncontrolled dependencies between hardware and software parts. In order to overcome these problems, we provide a design process that enables the partitioning based on a multiple criteria decision analysis in a late design phase. We illustrate the proposed approach and provide a proof-of concept on an industrial case study to validate the approach applicability.

  • 37.
    Seceleanu, Cristina Cerschi
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Johansson, M.
    ABB Corporate Research, Sweden.
    Suryadevara, J.
    Volvo Construction Equipment, Sweden.
    Sapienza, Gaetana
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research, Sweden.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research, Sweden.
    Ellevseth, S. -E
    ABB Corporate Research, Norway.
    Pettersson, Paul
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Analyzing a wind turbine system: From simulation to formal verification2017In: Science of Computer Programming, ISSN 0167-6423, E-ISSN 1872-7964, Vol. 133, p. 216-242Article in journal (Refereed)
    Abstract [en]

    Many industrial systems are hybrid by nature, most often being made of a discrete controller that senses and regulates the execution of a plant characterized by continuous dynamics. Examples of such systems include wind turbines that convert wind energy into electrical energy. Designing industrial control systems is challenging, due to the mixed nature of requirements (functional, timing, etc.) as well as due to the complexity stemming from the interaction of the controller with the plant. Model-based techniques help in tackling the design challenges, whereas methods such as simulation with tools like MATLAB/Simulink can be employed for analysis. Although practical, these methods alone cannot ensure full predictability, due to the fact that they cannot guarantee system properties for all possible executions of the system model. In order to ensure that the system will behave as expected under any operational circumstance, formal verification and validation procedures need to be added to the actual development process. In this paper, we propose an extension of the iFEST (industrial Framework for Embedded Systems Tools) process and platform for embedded systems design with model-based testing using MaTeLo, and model checking time-dependent requirements with the UPPAAL tool, as means of increasing the confidence in the system's behavior. To show the feasibility of the techniques on industrially-sized systems, we analyze a wind turbine industrial prototype model against functional and timing requirements. We capture the execution semantics of the plant and controller components of the wind turbine via logical clocks and constraints expressed in the clock constraint specification language (CCSL) of UML MARTE, after which we construct real-time models amenable to model checking, by mapping the timed behavior (expressed in CCSL) of the real-time components of the wind turbine, onto timed automata. Our work is a first application on an industrial wind turbine system of complementary methods for formal analysis, that is, model-based testing, and model checking a mathematically tractable system abstraction based on data obtained by simulating the system with MATLAB/Simulink. We also discuss relevant modeling and verification challenges encountered during our experiences with the wind turbine system.

  • 38.
    Seceleanu, Cristina
    et al.
    Åbo Akademi, TUCS, Finland .
    Seceleanu, Tiberiu
    University of Turku, Finland.
    Modular Design of Reactive Systems2004In: Proceedings - International Computer Software and Applications ConferenceVolume 1, 2004, 2004, p. 265-271Conference paper (Refereed)
    Abstract [en]

    We concentrate on two major aspects of reactive system design: behavior control and modularity. These are studied from a formal point of view, within the framework of action systems. The traditional interleaving paradigm is completed with a new barrier synchronization mechanism. This is achieved by introducing a new parallel composition operator, applicable to both discrete and hybrid models. While offering improvements with respect to control and modularity, the approach uses the correctness preserving mechanisms provided by the underlying reasoning environment.

  • 39.
    Seceleanu, Cristina
    et al.
    Åbo Akademi, Turku, Finland.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering. University of Turku, Finland.
    Synchronization Can Improve Reactive Systems Control and Modularity2004In: Journal of Universal Computer Science (JUCS), ISSN 0958-695X, Vol. 10, no 10, p. 1429-1468Article in journal (Refereed)
    Abstract [en]

    We concentrate on two major aspects of reactive system design: behavior control and modularity. These are studied from a formal point of view, within the framework of action systems. The traditional interleaving paradigm is completed with a barrier synchronization mechanism. This is achieved by introducing a new parallel composition operator, applicable to both discrete and hybrid models. While offering improvements with respect to control and modularity, the approach uses the correctness preserving mechanisms provided by the underlying reasoning environment.

  • 40.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research Centre, Sweden.
    Complex Systems: Simply, Improve Life2015In: Proceedings - International Computer Software and Applications Conference, 2015, p. 49-49Conference paper (Other academic)
    Abstract [en]

    Cyber-Physical Systems, building on embedded systems and ICT are large complex systems that pose challenges at multiple stages, out of which we mention here design, ownership and utilization. These systems are more and more penetrating our every-day life, impacting on multiple aspects of our activities. In spite of their complexity, or due to that, these systems are offering new opportunities for improving the quality of our lives, simplify our work while helping us to improve the results, and provide support for longer life-spans. 

  • 41.
    Seceleanu, Tiberiu
    et al.
    ABB.
    Crnkovic, Ivica
    Mälardalen University, School of Innovation, Design and Engineering.
    Seceleanu, Cristina
    Mälardalen University, School of Innovation, Design and Engineering.
    Transaction level control for application execution on the SegBus Platform2009In: Proceedings - International Computer Software and Applications Conference, vol. 1, 2009, 2009, p. 537-542Conference paper (Refereed)
    Abstract [en]

    We define here a simple, low level control procedure definition, to support application implementation on a particular multiprocessor platform, namely the SegBus segmented bus. The approach considers communication as data package transactions from one device to another. It takes into consideration the platform characteristics and requires details of application partitioning and mapping on platform resources. The dependency between operations are extracted from a SDFlike representation, and the actual control code is produced as “application-dependent” VHDL code, grouped in so-called snippets, application and platform instance dependent. The obtained code is inserted in a specific section of a (segmentor central level) arbiter. We illustrate the application of our approach on a small implementation example.

  • 42.
    Seceleanu, Tiberiu
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Leppanen, Ville
    University of Turku.
    Nevalainen, Olli
    University of Turku.
    Improving the Performance of Bus Platforms byMeans of Segmentation and Optimized Resource Allocation2009In: EURASIP Journal on Embedded Systems, no Article ID 867362Article in journal (Refereed)
  • 43.
    Seceleanu, Tiberiu
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sapienza, Gaetana
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Tool Integration Framework for Sustainable Embedded Systems Development2013In: Computer, ISSN 0018-9162, E-ISSN 1558-0814, Vol. 46, no 11, p. 68-71Article in journal (Refereed)
    Abstract [en]

    Tool integration in the context of embedded systems development and maintenance is challenging due to such systems' lengthy life cycles and adaptability to process specifications. The iFEST frameworkprovides flexibility in development processes and extends support for long product life cycles.

  • 44.
    Seceleanu, Tiberiu
    et al.
    Purdue University, United States .
    Subramanyan, R.
    University ca'Foscari, Italy .
    Seceleanu, Cristina
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    McMillin, B.
    Missouri University of Science and Technology, United States .
    Message from ECpE Symposium Organizing Committee2015In: Proceedings - International Computer Software and Applications ConferenceVolume 2, 2015, p. 4-4, article id 7273589Conference paper (Other academic)
  • 45.
    Shah, Kunjesh
    et al.
    Jönköping University.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Gidlund, Mikael
    ABB CRC.
    Design and Implementation of a WirelessHART Simulator for Process Control2010In: / [ed] IEEE, 2010, p. 221-224Conference paper (Refereed)
    Abstract [en]

    The WirelessHART protocol is one of the most promising standards for wireless communication in industrial automation plant systems. Control processes and the communication between them must be scheduled appropriately, such that the I/O data is correlated. In large networks, selecting a suitable schedule is a long and error prone exercise. This research report illustrates the design and realization of a WirelessHART system development tool, meant to support the design decisions in communication and processing scheduling. A simulator of such a system is built, to preview the resulting system performance. The purpose of designing the simulator is to support a more efficient usage of the timing specifications, and to offer collision free communication between network devices. The tool allows the development of the system starting from control loop levels, and provides information of possible errors in dataflow dependencies and network access conflicts.

  • 46.
    Suryadevara, Jagadish
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sapienza, Gaetana
    ABB Corporate Research, Norway.
    Seceleanu, Cristina
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Seceleanu, Tiberiu
    ABB Corporate Research, Norway.
    Elleveseth, Stein-Erik
    ABB Corporate Research, Norway.
    Pettersson, Paul
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Wind Turbine System: An Industrial Case Study in Formal Modeling and Verification2014In: Communications in Computer and Information Science, Volume 419 CCIS, 2014, p. 229-245Conference paper (Refereed)
    Abstract [en]

    In the development of embedded systems, the formal analysis of system artifacts, such as structural and behavioral models, helps the system engineers to understand the overall functional and timing behavior of the system. In this case study paper, we present our experience in applying formal verification and validation (V&V) techniques, we had earlier proposed, for an industrial wind turbine system (WTS). We demonstrate the complementary benefits of formal verification in the context of existing V&V practices largely based on simulation and testing. We also discuss some modeling trade-offs and challenges we have identified with the case-study, which are worth being emphasized. One issue is related, for instance, to the expressiveness of the system artifacts, in view of the known limitations of rigorous verification, e.g. model-checking, of industrial systems.

  • 47.
    Wolvers, Ronald
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering. IS (Embedded Systems).
    Embedded Systems Design Flows: Integrating Requirements Authoring and Design Tools2013Conference paper (Refereed)
    Abstract [en]

    In the modern practical reality there are many different tools being used in the various phases of the system development lifecycle. Every tool employs its own underlying metamodel and these metamodels tend to vary greatly in size and complexity, making them difficult to integrate. One solution to overcome this problem is to build a tool integration framework that is based on a single, shared metamodel. We introduce here an OSLC based approach to integration. To validate the framework, an industrial case has been carried out, using several embedded systems tools. To expose tools internal data through Web services, a tool adaptor is needed. This work reports on the development of such an adaptor for the Requirements Management module of HP ALM, as used in the industrial case.

  • 48.
    Zakupszki, Andras
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Pichetpongsa, Nuttapon
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research and Mälardalen University, Västerås, Sweden.
    Scheduling and simulating wireless HART systems2014In: Proceedings: 40th Euromicro Conference Series on Software Engineering and Advanced Applications, SEAA 2014, 2014, p. 318-319Conference paper (Refereed)
    Abstract [en]

    Control processes and the communication between them must be scheduled appropriately, such that the I/O data is correlated. Here, we illustrate the design and realization of a Wireless HART system development tool, meant to support design decisions in communication and processing scheduling.

1 - 48 of 48
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