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  • 1.
    Abdullah, Syed Md Jakaria
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Moghaddami Khalilzad, Nima
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Towards Implementation of Virtual-Clustered Multiprocessor Scheduling in Linux2013Ingår i: Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, SIES 2013, 2013, s. 97-100Konferensbidrag (Refereegranskat)
    Abstract [en]

    Cluster based multiprocessor scheduling can be seen as a hybrid approach combining benefits of both partitioned and global scheduling. Virtual clustering further enhances it by providing dynamic cluster resource allocation and applying hierarchical scheduling techniques. Over the years, the study of virtual cluster scheduling has been limited to theoretical analysis. In this paper, we present our initial ideas about implementing virtual cluster scheduling in Linux. The purpose of this implementation is twofold: (i) we would like to demonstrate the feasibility of its implementation in an operating system, without modifying the kernel source code, (ii) we present practical insights on the overhead of implementing this framework.

  • 2.
    Afshar, Sara
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Resource Sharing under Server-based Multiprocessor SchedulingIngår i: 33rd IEEE Real-Time Systems Symposium (RTSS'12), Work-in-Progress (WiP) sessionKonferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper, we investigate a mechanism for handling resource sharing among tasks under a server-based scheduling technique in multiprocessor platforms, which combines partitioned and global scheduling to benefit a better scheduling method compared to conventional techniques.

  • 3.
    Afshar, Sara
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Bril, R. J.
    Technische Universiteit Eindhoven, Eindhoven, Netherlands .
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Flexible spin-lock model for resource sharing in multiprocessor real-time systems2014Ingår i: Proc. IEEE Int. Symp. Ind. Embedded Syst., SIES, 2014, s. 41-51Konferensbidrag (Refereegranskat)
    Abstract [en]

    Various approaches can be utilized upon resource locking for mutually exclusive resource access in multiprocessor platforms. So far two conventional approaches exist for dealing with tasks that are blocked on a global resource in a multi-processor platform. Either the blocked task performs a busy wait, i.e. spins, at the highest priority level until the resource is released, or it is suspended. Although both approaches provide mutually exclusive access to resources, they can introduce long blocking delays to tasks, which may be unacceptable for many industrial applications. In this paper, we propose a general spin-based model for resource sharing in multiprocessor platforms in which the priority of the blocked tasks during spinning can be selected arbitrarily. Moreover, we provide the analysis for two selected spin-lock priorities and we show by means of a general comparison as well as specific examples that these solutions may provide a better performance for higher priority tasks.

  • 4.
    Afshar, Sara
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Bril, Reinder J.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Resource sharing in a hybrid partitioned/global scheduling framework for multiprocessors2015Ingår i: IEEE International Conference on Emerging Technologies and Factory Automation, ETFA, 2015Konferensbidrag (Refereegranskat)
    Abstract [en]

    For resource-constrained embedded real-time systems, resource-efficient approaches are very important. Such an approach is presented in this paper, targeting systems where a critical application is partitioned on a multi-core platform and the remaining capacity on each core is provided to a noncritical application using resource reservation techniques. To exploit the potential parallelism of the non-critical application, global scheduling is used for its constituent tasks. Previously, we enabled intra-application resource sharing for such a framework, i.e. each application has its own dedicated set of resources. In this paper, we enable inter-application resource sharing, in particular between the critical application and the non-critical application. This effectively enables resource sharing in a hybrid partitioned/global scheduling framework on multiprocessors. For resource sharing, we use a spin-based synchronization protocol. We derive blocking bounds and extend existing schedulability analysis for such a system.

  • 5.
    Afshar, Sara
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Bril, Reinder J.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Technische Universiteit Eindhoven, Eindhoven, Netherlands.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Resource Sharing Under Global Scheduling with Partial Processor Bandwidth2015Ingår i: 2015 10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015 - Proceedings, 2015, s. 195-206Konferensbidrag (Refereegranskat)
    Abstract [en]

    Resource efficient approaches are of great importance for resource constrained embedded systems. In this paper, we present an approach targeting systems where tasks of a critical application are partitioned on a multi-core platform and by using resource reservation techniques, the remaining bandwidth capacity on each core is utilized for one or a set of non-critical application(s). To provide a resource efficient solution and to exploit the potential parallelism of the extra applications on the multi-core processor, global scheduling is used to schedule the tasks of the non-critical applications. Recently a specific instantiation of such a system has been studied where tasks do not share resources other than the processor. In this paper, we enable semaphore-based resource sharing among tasks within critical and non-critical applications using a suspension-based synchronization protocol. Tasks of non-critical applications have partial access to the processor bandwidth. The paper provides the systems schedulability analysis where blocking due to resource sharing is bounded. Further, we perform experimental evaluations under balanced and unbalanced allocation of tasks of a critical application to cores.

  • 6.
    Afshar, Sara
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    J. Bril, Reinder
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Per Processor Spin-Lock Priority for Partitioned Multiprocessor Real-Time Systems2014Rapport (Övrigt vetenskapligt)
    Abstract [en]

    Two traditional approaches exist for a task that is blocked on a global resource; a task either performs a non-preemptive busy wait, i.e., spins, or suspends and releases the processor. Previously, we have shown that both approaches can be viewed as spinning either at the highest priority HP or at the lowest priority on the processor LP, respectively. Based on this view, previously we have generalized a task's blocking behavioral model, as spinning at any arbitrary priority level. In this paper, we focus on a particular class of spin-lock protocols from the introduced flexible spin-lock model where spinning is performed at a priority equal to or higher than the highest local ceiling of the global resources accessed on a processor referred to as CP spin-lock approach. In this paper, we assume that all tasks of a specific processor are spinning on the same priority level. Given this class and assumption, we show that there exists a spin-lock protocol in this range that dominates the classic spin-lock protocol which tasks spin on highest priority level (HP). However we show that this new approach is incomparable with the CP spin-lock approach. Moreover, we show that there may exist an intermediate spin-lock approach between the priority used by CP spin-lock approach and the new introduced spin-lock approach that can make a task set schedulable when those two cannot. We provide an extensive evaluation results comparing the HP, CP and the new proposed approach.

  • 7.
    Afshar, Sara
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    J. Bril, Reinder
    Technische Universiteit Eindhoven, Eindhoven, The Netherlands.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Per Processor Spin-Lock Priority for Partitioned Multiprocessor Real-Time Systems2017Ingår i: Leibniz Transactions on Embedded Systems, ISSN 2199-2002, nr 2Artikel i tidskrift (Övrigt vetenskapligt)
    Abstract [en]

    Two traditional approaches exist for a task that is blocked on a global resource; a task either performs a non-preemptive busy wait, i.e., spins, or suspends and releases the processor. Previously, we have shown that both approaches can be viewed as spinning either at the highest priority HP or at the lowest priority on the processor LP, respectively. Based on this view, previously we have generalized a task's blocking behavioral model, as spinning at any arbitrary priority level. In this paper, we focus on a particular class of spin-lock protocols from the introduced flexible spin-lock model where spinning is performed at a priority equal to or higher than the highest local ceiling of the global resources accessed on a processor referred to as CP spin-lock approach. In this paper, we assume that all tasks of a specific processor are spinning on the same priority level. Given this class and assumption, we show that there exists a spin-lock protocol in this range that dominates the classic spin-lock protocol which tasks spin on highest priority level (HP). However we show that this new approach is incomparable with the CP spin-lock approach. Moreover, we show that there may exist an intermediate spin-lock approach between the priority used by CP spin-lock approach and the new introduced spin-lock approach that can make a task set schedulable when those two cannot. We provide an extensive evaluation results comparing the HP, CP and the new proposed approach.

  • 8.
    Afshar, Sara
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Integrating independently developed real-time applications on a shared multi-core architecture2013Ingår i: ACM SIGBED Review, v. 10, n. 3, 2013, s. 49-56Konferensbidrag (Refereegranskat)
    Abstract [en]

    The shift towards multi-core platforms has become inevitable from an industry perspective, therefore proper techniques are needed to deal with challenges related to this migration from single core architectures to a multi-core architecture. One of the main concerns for the system developers in this context is the migration of legacy real-time systems to multi-core architectures. To address this concern and to simplify migration, independently developed subsystems are abstracted with an interface, such that when working with multiple independently-developed subsystems to be integrated on a shared platform, one does not need to be aware of information or policies used in other subsystems in order to determine subsystem-level schedulability. Instead schedulability can be checked through their interfaces at the time of integration on a shared multi-core architecture. In this paper we propose a solution for the case where some of the independently-developed subsystems are distributed over more than one processor and we propose an approach to generate interfaces of subsystems that may share mutually exclusive resources.

  • 9.
    Afshar, Sara
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Semi-partitioning under a Blocking-Aware Task Allocation2015Ingår i: Proceedings - Real-Time Systems Symposium, 2015, s. 379-379Konferensbidrag (Refereegranskat)
    Abstract [en]

    Semi-partitioned scheduling is a resource efficient scheduling approach compared to the conventional multiprocessor scheduling approaches in terms of system utilization and migration overhead. Semi-partitioned scheduling can better utilize processor bandwidth compared to the partitioned scheduling while introducing less overhead compared to the global scheduling. Various techniques have been proposed to schedule tasks in a semi-partitioned environment, however, they have used blockingagnostic allocation mechanisms in presence of resource sharing protocols. Since, the allocation mechanism can highly affect the system schedulability, in this paper we provide a blocking-aware allocation mechanism for semi-partitioned scheduling framework under a suspension-based resource sharing protocol. We have applied new heuristics for sorting the tasks in the algorithm that shows improvements upon system schedulability. Finally, we present our preliminary results.

  • 10.
    Afshar, Sara
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Khalilzad, Nima
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Bril, Reinder J.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Universiteit Eindhoven, Eindhoven, Netherlands.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Intra-component Resource Sharing on a Virtual Multiprocessor Platform2016Ingår i: ACM SIGBED Review: Special Issue on 8th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems, 2016, s. 31-32Konferensbidrag (Refereegranskat)
    Abstract [en]

    Component-based software development facilitates the development process of large and complex software systems. By the advent of multiprocessors, the independently developed components can be integrated on a multi-core platform to achieve an efficient use of system hardware and a decrease in system power consumption and costs. In this paper, we consider a virtual multiprocessor platform where each component can be dynamically allocated to any set of processors of the platform with a maximum concurrency level. Global-EDF is used for intra-component scheduling. The existing analysis for such systems have assumed that tasks are independent. In this paper, we enable intra-component resource sharing for this platform. We investigate using a spin-based resource sharing protocol with the accompanying analysis that extends the existing analysis for independent tasks. We briefly illustrate and evaluate our initial results with an example.

  • 11.
    Afshar, Sara Zargari
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    J. Bril, Reinder
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Technische Universiteit Eindhoven, Eindhoven, Netherlands.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    An optimal spin-lock priority assignment algorithm for real-time multi-core systems2017Ingår i: The 23th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'17, 2017, artikel-id 8046310Konferensbidrag (Refereegranskat)
    Abstract [en]

    Support for exclusive access to shared (global) resources is instrumental in the context of embedded real-time multi-core systems, and mechanisms for achieving such access must be deterministic and efficient. There exist two traditional approaches for multiprocessors when a task requests a global resource that is locked by a task on a remote core: a spin-based approach, i.e. non-preemptive busy waiting for the resource to become available, and a suspension-based approach, i.e. the task relinquishes the processor. A suspension-based approach can be viewed as a spin-based approach where the lowest priority on a core is used during spinning, similar to a non-preemptive spin-based approach where the highest priority on a core is used. By taking such a view, we previously provided a general model for spinning, where any arbitrary priority can be used for spinning, i.e. from the lowest to the highest priority on a core. Targeting partitioned fixed-priority preemptive scheduled multiprocessors and spin-based approaches that use a fixed priority for spinning per core for all tasks, we aim at increasing the schedulability of multiprocessor systems by using the spin-lock priority per core as parameter. In this paper, we present (i) a generalization of the traditional worst-case response-time analysis for non-preemptive spin-based approaches addressing an arbitrary but fixed spin-lock priority per core, (ii) an optimal spin-lock priority assignment (OSPA) algorithm per core, i.e. an algorithm that will find a fixed spin-lock priority per core that will make the system schedulable, whenever such an assignment exists and, (iii) comparative evaluations of the OSPA algorithm with the spin-based and suspension-based approaches where OSPA showed up to 38% improvement compared to both approaches.

  • 12.
    Aglianò, Simone
    et al.
    University of Catania, Catania, Italy.
    Ashjaei, Seyed Mohammad Hossein
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Lo Bello, Lucia
    University of Catania, Catania, Italy.
    Resource Management and Control in Virtualized SDN Networks2018Ingår i: CSI International Symposium on Real-Time and Embedded Systems and Technologies REST'18, 2018, s. 47-53Konferensbidrag (Refereegranskat)
    Abstract [en]

    Software defined networking and network virtual-ization are widely considered promising techniques for reducing the complexity of network management in many contexts that require high Quality of Service (QoS) and the support for heterogeneous architectures. In this paper we address a network architecture, here called a virtualized SDN network, that combines the benefits of SDN and virtualization. To cope with the demand for efficiently sharing a platform among several services, here a resource management mechanism to reserve and control network resources among various services in the virtualized SDN networks is proposed. The mechanism is implemented on an SDN controller and a set of experiments show the effectiveness of the proposed approach.

  • 13.
    Almeida, Luis
    et al.
    University of Porto, Portugal.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Pedreiras, Paulo
    University of Aveiro, Portugal.
    Managing end-to-end resource reservations2014Ingår i: 7th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems CRTS'14, 2014Konferensbidrag (Refereegranskat)
  • 14.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Almeida, Luis
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    MTU Assignment in a Master-Slave Switched Ethernet Network2013Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper, we investigate the problem of selecting the Maximal Transmission Unit (MTU) size that maximizes the schedulability of real-time messages. We focus on a bandwidth-efficient master-slave switched Ethernet protocol, namely the FTT-SE protocol. We propose an algorithm to find the MTU for each message in order to maximize the schedulability of the messages. Moreover, we evaluate our proposed algorithm and we show that setting the MTU for messages using the algorithm increases the schedulability of messages compared with assigning the MTU to the maximum value that the protocol can support.

  • 15.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Almeida, Luis
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. University of Porto, Porto, Portugal .
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    MTU Configuration for Real-Time Switched Ethernet Networks2016Ingår i: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 70, s. 15-25Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this paper, we show that in real-time switched Ethernet networks reducing the Maximum Transmission Unit (MTU) size may cause an increase or decrease in the response time of messages. This contradicting behavior arises an optimization problem for configuring the MTU size. We formulate the optimization problem in the context of the multi-hop HaRTES architecture, which is a hard real-time Ethernet protocol. As part of the solution, we propose a search-based algorithm to achieve optimum solutions. We modify the algorithm by presenting two techniques to reduce the search space. Then, we propose a heuristic algorithm with a pseudo-polynomial time complexity based on the search-based algorithm. We perform several experiments, and we show that the proposed heuristic results in an improvement regarding messages response times, compared with configuring the MTU to the maximum or minimum values. Moreover, we show in small network configurations that the heuristic performs as good as the search-based algorithm in many cases.

  • 16.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Almeida, Luis
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Performance Analysis of Master-Slave Multi-Hop Switched Ethernet Networks2013Ingår i: Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, SIES 2013, 2013, s. 280-289Konferensbidrag (Refereegranskat)
    Abstract [en]

    There is an increasing trend towards using switched Ethernet in real-time distributed systems due to features like absence of collisions and high throughput. Nevertheless, a few problems persist, in particular related to priority inversion and limited length in queues. In this paper we focus on a protocol which uses a master-slave technique over standard switched Ethernet in order to overcome such problems, namely FTT-SE protocol. We present an improved response time analysis for such a network and we compare, analytically and with simulations, the results achieved with Network Calculus on a worst-case scenario. We show that our proposed response time analysis gives tighter bounds compared to Network Calculus. Moreover, we compare the performance of different solutions to scale the FTT-SE protocol with respect to the bandwidth utilization. Finally, we propose a new architecture to improve the average performance of master-slave switched Ethernet networks.

  • 17.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Malardalen Univ, Malardalen Real Time Res Ctr MRTC, POB 883, SE-72123 Vasteras, Sweden..
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Malardalen Univ, Malardalen Real Time Res Ctr MRTC, POB 883, SE-72123 Vasteras, Sweden..
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Malardalen Univ, Malardalen Real Time Res Ctr MRTC, POB 883, SE-72123 Vasteras, Sweden..
    SEtSim: A modular simulation tool for switched Ethernet networks2016Ingår i: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 65, s. 1-14Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Using high bandwidth network technologies in real-time applications, for example in automotive systems, is rapidly increasing. In this context, switched Ethernet-based protocols are becoming more popular due to their features such as providing a collision-free domain for transmission of messages. Moreover, switched Ethernet is a mature technology. Several protocols based on switched Ethernet have been proposed over the years, tuned for time critical applications. However, research for improving the features and performance of these protocols is still on-going. In order to evaluate the performance of early stage proposed protocols, the mathematical analysis and/or experiments are required. However, performing an experiment for complex network topologies with a large set of messages is not effortless. Therefore, using a simulation based approach for evaluating a protocol's performance and/or properties is highly useful. As a response to this we have developed a simulator, called SEtSim, for switched Ethernet networks. SEtSim is developed based on Simulink, and it currently supports different network topologies of the FIT-SE protocol as well as Ethernet AVB protocol. However, the kernel of SEtSim is designed such that it is possible to add and integrate other switched Ethernet-based protocols. In this paper, we describe the design of SEtSim and we show its scalability.

  • 18.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik. Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik. Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik. Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    SEtSim: A Modular Simulation Tool for Switched Ethernet Networks2014Rapport (Övrigt vetenskapligt)
    Abstract [en]

    Using high bandwidth network technologies in real-time applications, for example in automotive systems, is rapidly increasing. In this context, switched Ethernet-based protocols are becoming more popular due to their features such as providing a collision-free domain for transmission of messages. Moreover, switched Ethernet is a mature technology. Several protocols based on switched Ethernet have been proposed over the years, tuned for time critical applications. However, research for improving the features and performance of these protocols is still on-going. In order to evaluate the performance of early stage proposed protocols, the mathematical analysis and/or experiments are required. However, performing an experiment for complex network topologies with a large set of messages is not effortless. Therefore, using a simulation based approach for evaluating a protocol's performance and/or properties is highly useful. As a response to this we have, based on Simulink, developed a simulator, called SEtSim, for switched Ethernet networks. SEtSim currently supports different network topologies of the FTT-SE protocol, a master-slave protocol designed for standard Ethernet switches, as well as Ethernet AVB protocol. However, the kernel of SEtSim is designed such that it is possible to add and integrate other switched Ethernet-based protocols. In this paper, we describe the design of SEtSim and we show its scalability.

  • 19.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik.
    The Design and Implementation of a Simulator for Switched Ethernet Networks2012Ingår i: 3rd International Workshop on Analysis Tools andMethodologies for Embeddedand Real-time Systems / [ed] Tommaso Cucinotta and Giuseppe Lipari, 2012, s. 57-62Konferensbidrag (Refereegranskat)
    Abstract [en]

    In the context of Switched Ethernet, the Flexible Time-Triggered Switched Ethernet protocol (FTT-SE) was proposed to overcome the limitations and related problems of using COTS switches in real-time networks, such as overflow of switch queues due to uncontrolled arrival of packets. Although the FTT-SE protocol has been validated by several experiments on real applications, evaluation of different architectures as well as evaluation of large scale networks is not straightforward. Therefore, a simulator to evaluate different network architectures based on the FTT-SE protocol is useful. In this paper we present such a simulator. We address the extended FTT-SE protocol using multiple switches and we present a modular simulator based on Simulink/Matlab to visualize message transmissions and to evaluate end-to-end delay bounds of messages.

  • 20.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Almeida, Luis
    University of Porto.
    Marau, Ricardo
    University of Porto.
    A Compact Approach to Clustered Master-Slave Ethernet Networks2012Ingår i: IEEE International Workshop on Factory Communication Systems - Proceedings, WFCS, 2012, s. 157-160Konferensbidrag (Refereegranskat)
    Abstract [en]

    Ethernet switches are increasingly used in real-time distributed systems as a technical solution to guarantee the timeliness in communications. However, there are still limitations related to real-time behavior caused by the limited number of priority levels and the possibility of memory overruns with consequent message losses. These limitations can be eliminated using a master/slave technique such as proposed by the FTT paradigm. This led to the FTT-SE protocol that schedules transmissions centrally in a master node. While this protocol has already been well studied and investigated for small networks with a single switch, its extension to larger networks is still an open issue. In this paper we propose a compact clustered solution to scale the FTT-SE protocol to networks of multiple switches by organizing the network in sub-networks composed of one master and one switch each and which can be connected directly, without bridges. This paper also shows how the timeliness of the traffic can still be enforced. The validation is currently on-going.

  • 21.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Pedreiras, Paulo
    University of Aveiro, Portugal.
    Bril, Reinder J.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Almeida, Luis
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Reduced Buffering Solution for Multi-Hop HaRTES Switched Ethernet Networks2014Ingår i: The 20th IEEE International Conference on embedded and Real-Time Computing Systems and Applications RTCSA'14, 2014, s. Article number 6910504-Konferensbidrag (Refereegranskat)
    Abstract [en]

    In the context of switched Ethernet networks, multi-hop communication is essential as the networks in industrial applications comprise a high amount of nodes, that is far beyond the capability of a single switch. In this paper, we focus on multi-hop communication using HaRTES switches. The HaRTES switch is a modified Ethernet switch that provides real-time traffic scheduling, dynamic Quality-of-Service and temporal isolation between real-time and non-real-time traffic. Herein, we propose a method, called Reduced Buffering Scheme, to conduct the traffic through multiple HaRTES switches in a multi-hop HaRTES architecture. In order to enable the new scheduling method we propose to modify the HaRTES switch structure. Moreover, we develop a response time analysis for the new method. We also compare the proposed method with a method previously proposed, called Distributed Global Scheduling, based on their traffic response times. We show that, the new method forwards all types of traffic including the highest, the medium and the lowest priority, faster than the previous method in most of the cases. Furthermore, we show that the new method performs even better for larger networks compared with the previous one.

  • 22.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Rodriguez-Navas, Guillermo
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Universitat de les Illes Balears, Spain.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Implementing a Clock Synchronization Protocol on a Multi-Master Switched Ethernet Network2013Konferensbidrag (Refereegranskat)
    Abstract [en]

    The interest to use Switched Ethernet technologies in real-time communication is increasing due to its absence of collisions when transmitting messages. Nevertheless, using COTS switches affect the timeliness guarantee inherent in potentially overflowing internal FIFO queues. In this paper we focus on a solution, called the FTT-SE protocol, which is developed based on a master-slave technique. Recently, an extension of the FTT-SE protocol has been proposed where the transmission of messages are controlled using multiple master nodes. In order to guarantee the correctness of the protocol, the masters should be timely synchronized. Therefore, in this paper we investigate using a clock synchronization protocol, based on the IEEE 1588 standard, among master nodes and we study the effects of this protocol on the network performance. In addition, we present a formal verification of this solution by means of model checking to prove the correctness of the FTT-SE protocol when the clock synchronization protocol is applied.

  • 23.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Du, Yong
    Almeida, L.
    University of Porto, Porto, Portugal .
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dynamic reconfiguration in HaRTES switched ethernet networks2016Ingår i: IEEE International Workshop on Factory Communication Systems - Proceedings, WFCS, 2016, artikel-id Article number 7496510Konferensbidrag (Refereegranskat)
    Abstract [en]

    The ability of reconfiguring a system during runtime is essential for dynamic real-time applications in which resource usage is traded online for quality of service. The HaRTES switch, which is a modified Ethernet switch, holds this ability for the network resource, and at the same time it provides hard real-time support for both periodic and sporadic traffic. Although the HaRTES switch technologically caters this ability, a protocol to actually perform the dynamic reconfiguration is missing in multi-hop HaRTES networks. In this paper we introduce such a protocol that is compatible with the traffic scheduling method used in the architecture. We prove the correctness of the protocol using a model checking technique. Moreover, we conduct a set of simulation experiments to show the performance of the protocol and we also show that the reconfiguration process is terminated within a bounded time. 

  • 24.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Khalilzad, Nima
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. IS (Embedded Systems).
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Sander, Ingo
    Royal Institute of Technology, Sweden.
    Almeida, Luis
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Designing End-to-end Resource Reservations in Predictable Distributed Embedded Systems2017Ingår i: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 53, nr 6, s. 916-956Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Contemporary distributed embedded systems in many domains have become highly complex due to ever-increasing demand on advanced computer controlled functionality. The resource reservation techniques can be effective in lowering the software complexity, ensuring predictability and allowing flexibility during the development and execution of these systems. This paper proposes a novel end-to-end resource reservation model for distributed embedded systems. In order to support the development of predictable systems using the proposed model, the paper provides a method to design resource reservations and an end-to-end timing analysis. The reservation design can be subjected to different optimization criteria with respect to runtime footprint, overhead or performance. The paper also presents and evaluates a case study to show the usability of the proposed model, reservation design method and end-to-end timing analysis. 

  • 25.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Liu, Meng
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Mifdaoui, A.
    University of Toulouse, France.
    Almeida, L.
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik.
    Worst-case delay analysis of master-slave switched ethernet networks2012Ingår i: Proceeings of the 2nd International Workshop on Worst-Case Traversal Time: Proceeding, 2012, s. 15-21Konferensbidrag (Refereegranskat)
    Abstract [en]

    Switched Ethernet is increasingly used in real-time communication due to its intrinsic features such as micro segmentation and high throughput. However, COTS switches may impose long blocking times due to their FIFO queues and can also experience buffer overflow in outgoing queues due to uncontrolled packets arrival. The FTT-SE protocol uses a Master-Slave technique to overcome the COTS switch limitations in real-time applications. Recently, we extended the protocol for large scale networks and in this paper we present the worst-case delay analysis using the Network Calculus formalism for such a network. Moreover, we assess the end-to-end delay of traffic with simulation concluding that the obtained analytical results present a good match with the observed delays, providing uppers bounds that vary between 0% and 50% above the maximum measured values. © 2012 ACM.

  • 26.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Almeida, Luis
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    End-to-end Resource Reservations in Distributed Embedded Systems2016Ingår i: Proceedings - 2016 IEEE 22nd International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2016, 2016, s. 1-11, artikel-id 7579921Konferensbidrag (Refereegranskat)
    Abstract [en]

    The resource reservation techniques provide effective means to lower the software complexity, ensure predictability and allow flexibility during the development and execution of complex distributed embedded systems. In this paper we propose a new end-to-end resource reservation model for distributed embedded systems. The model is comprehensive in such a way that it supports end-to-end resource reservations on distributed transactions with various activation patterns that are commonly used in industrial control systems. The model allows resource reservations on processors and real-time network protocols. We also present timing analysis for the distributed embedded systems that are developed using the proposed model. The timing analysis computes the end-to-end response times as well as delays such as data age and reaction delays. The presented analysis also supports real-time networks that can autonomously initiate transmissions. Such networks are not supported by the existing analyses. We also include a case study to show the usability of the model and end-to-end timing analysis with resource reservations.

  • 27.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    End-to-end Resource Reservation Model2016Manuskript (preprint) (Övrigt vetenskapligt)
  • 28.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Patti, Gaetano
    University of Catania, Italy.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Alderisi, Giuliana
    University of Catania, Italy.
    Lo Bello, Lucia
    University of Catania, Italy.
    Schedulability Analysis of Ethernet Audio Video Bridging Networks with Scheduled Traffic Support2017Ingår i: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 53, nr 4, s. 526-577Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    The IEEE Audio Video Bridging (AVB) technology is nowadays under consideration in several automation domains, such as, automotive, avionics, and industrial communications. AVB offers several benefits, such as open specifications, the existence of multiple providers of electronic components, and the real-time support, as AVB provides bounded latency to real-time traffic classes. In addition to the above mentioned properties, in the automotive domain, comparing with the existing in-vehicle networks, AVB offers significant advantages in terms of high bandwidth, significant reduction of cabling costs, thickness and weight, while meeting the challenging EMC/EMI requirements. Recently, an improvement of the AVB protocol, called the AVB ST, was proposed in the literature, which allows for supporting scheduled traffic, i.e., a class of time-sensitive traffic that requires time-driven transmission and low latency. In this paper, we present a schedulability analysis for the real-time traffic crossing through the AVB ST network. In addition, we formally prove that, if the bandwidth in the network is allocated according to the AVB standard, the schedulability test based on response time analysis will fail for most cases even if, in reality, these cases are schedulable. In order to provide guarantees based on analysis test a bandwidth over-reservation is required. In this paper, we propose a solution to obtain a minimized bandwidth over-reservation. To the best of our knowledge, this is the first attempt to formally spot the limitation and to propose a solution for overcoming it. The proposed analysis is applied to both the AVB standard and the AVB ST. The analysis results are compared with the results of several simulative assessments, obtained using OMNeT++, on both automotive and industrial case studies. The comparison between the results of the analysis and the simulation ones shows the effectiveness of the analysis proposed in this work.

  • 29.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Pedreiras, P.
    University of Aveiro, Aveiro, Portugal .
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Almeida, L.
    University of Porto, Porto, Portugal.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Evaluation of dynamic reconfiguration architecture in multi-hop switched ethernet networks2014Ingår i: 19th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2014, 2014, s. Article number 7005322-Konferensbidrag (Refereegranskat)
    Abstract [en]

    On-the-fly adaptability and reconfigurability are recently becoming an interest in real-time communications. To assure a continued real-time behavior, the admission control with a quality-of-service mechanism is required, that screen all adaptation and reconfiguration requests. In the context of switched Ethernet networks, the FTT-SE protocol provides adaptive real-time communication. Recently, we proposed two methods to perform the online reconfiguration in multi-hop FTT-SE architectures. However, the methods lack the experimental evaluation. In this paper, we evaluate both methods in terms of the reconfiguration time. 

  • 30.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Pedreiras, P.
    DETI/IT, University of Aveiro, Aveiro, Portugal .
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Bril, Reinder J.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Technische Universiteit Eindhoven (TU/e), Netherlands .
    Almeida, L.
    Technische Universiteit Eindhoven (TU/e), Netherlands .
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Response time analysis of multi-hop HaRTES Ethernet Switch networks2014Ingår i: IEEE Int. Workshop Factory Commun. Syst. Proc. WFCS, 2014Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper we focus on micro-segmented switched-Ethernet networks with HaRTES switches. HaRTES switches provide synchronous and asynchronous real-time traffic scheduling, dynamic Quality-of-Service adaptation and transparent integration of real-time and non-real-time nodes. Herein we investigate the challenges of connecting multiple HaRTES switches in order to build multi-hop communication and we propose a method, named Distributed Global Scheduling, to handle the traffic forwarding in such an architecture while preserving the unique properties of the single HaRTES switch case. Moreover, we develop a response time analysis for the method. We also evaluate the level of pessimism embodied in the anal-ysis. Finally, we show the applicability of the proposed method in an industrial setting by applying it in an automotive case study.

  • 31.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Pedreiras, Paulo
    University of Aveiro, Portugal.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Almeida, Luis
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dynamic Reconfiguration in Multi-Hop Switched Ethernet Networks2014Ingår i: ACM SIGBED Review. Special Issue on 6th Workshop on Adaptive and Reconfigurable Embedded Systems (APRES 2014), ISSN 1551-3688, Vol. 11, nr 3, s. 62-65Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    The FTT-SE protocol provides adaptive real-time communication on Ethernet networks. To assure a continued real-time behavior, FTT-SE integrates admission control with a quality-of-service mechanism, which screen all adaptation and reconfiguration requests, accepting only those that do not compromise the system timeliness. The adaptability and reconfigurability have been deeply studied in the case of single switch FTT-SE architectures, whereas the extension of that for the multi-hop FTT-SE architecture was not yet investigated. Therefore, in this paper we study the challenges of enabling dynamic reconfiguration in multi-hop FTT-SE networks, we propose two methods (one centralized and one distributed) and we present a qualitative comparison between them.

  • 32.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Pedreiras, Paulo
    University of Aveiro, Portugal.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Almeida, Luis
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Supporting Multi-Hop Communications with HaRTES Ethernet Switches2013Konferensbidrag (Refereegranskat)
    Abstract [en]

    In this paper we identify the challenges of multi-hop communication when using a micro-segmented switched-Ethernet protocol with enhanced HaRTES switches. The HaRTES architecture has been explored in the scope of single-switch topology, and provides dynamic virtual channels that can be composed hierarchically and provide bounded latency together with temporal isolation. Herein we propose two different solutions regarding the traffic forwarding in multi-switch architectures, while maintaining the unique properties of the single HaRTES switch case. In the first approach, the traffic is buffered and scheduled sequentially in each hop. In the second solution the traffic is scheduled once and forwarded immediately through multiple switches without buffering. In this paper we present a brief comparison of both approaches and we report on the on-going work towards effective support to real-time communications in dynamic and complex Cyber-Physical Systems.

  • 33.
    Ashjaei, Mohammad
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. MRTC Malardalen Univ, Vasteras, Sweden..
    Silva, Luis
    DETI IT Univ Aveiro, Aveiro, Portugal..
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. MRTC Malardalen Univ, Vasteras, Sweden..
    Pedreiras, Paulo
    DETI IT Univ Aveiro, Aveiro, Portugal..
    Bril, Reinder J.
    Tech Univ Eindhoven TU E, Eindhoven, Netherlands..
    Almeida, Luis
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. MRTC Malardalen Univ, Vasteras, Sweden.;IT DEEC Univ Porto, Oporto, Portugal..
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. MRTC Malardalen Univ, Vasteras, Sweden..
    Improved Message Forwarding for Multi-Hop HaRTES Real-Time Ethernet Networks2016Ingår i: Journal of Signal Processing Systems, ISSN 1939-8018, E-ISSN 1939-8115, Vol. 84, nr 1, s. 47-67Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Nowadays, switched Ethernet networks are used in complex systems that encompass tens to hundreds of nodes and thousands of signals. Such scenarios require multi-switch architectures where communications frequently occur in multiple hops. In this paper we investigate techniques to allow efficient multi-hop communication using HaRTES switches. These are modified Ethernet switches that provide real-time traffic scheduling, dynamic bandwidth management and temporal isolation between real-time and non-real-time traffic. This paper addresses the problem of forwarding traffic in HaRTES networks. Two methods have been recently proposed, namely Distributed Global Scheduling (DGS) that buffers traffic between switches, and Reduced Buffering Scheme (RBS), that uses immediate forwarding. In this paper, we discuss the design and implementation of RBS within HaRTES and we carry out an experimental validation with a prototype implementation. Then, we carry out a comparison between RBS and DGS using worst-case response time analysis and simulation. The comparison clearly establishes the superiority of RBS concerning end-to-end response times. In fact, with sample message sets, we achieved reductions in end-to-end delay that were as high as 80 %.

  • 34.
    Balasubramanian, S. M. N.
    et al.
    Technische Universiteit Eindhoven, Eindhoven, Netherlands.
    Afshar, Sara
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Gai, P.
    Evidence Srl, Pisa, Italy.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    J. Bril, Reinder
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Practical challenges for FSLM2019Ingår i: Proceedings - 2018 IEEE 24th International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2018, Institute of Electrical and Electronics Engineers Inc. , 2019, s. 238-239, artikel-id 8607257Konferensbidrag (Refereegranskat)
    Abstract [en]

    The flexible spin-lock model (FSLM) unifies suspension-based and spin-based resource access protocols for partitioned fixed-priority preemptive scheduling based real-time multi-core platforms. Recent work has been done in defining the protocol for FSLM, providing schedulability analysis, and investigating the practical consequences of the theoretical model. FSLM complies to the AUTOSAR standard for the automotive industry, and prototype implementations of FSLM in the OSEK/VDX-complaint Erika Enterprise Real-Time Operating System have been realized. In this paper, we briefly describe some practical challenges to improve efficiency and generality. 

  • 35.
    Balasubramanian, S.M.N
    et al.
    Technische Universiteit Eindhoven, Eindhoven, Netherlands.
    Afshar, Sara Zargari
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Gai, Paolo
    Evidence Srl, Pisa, Italy.
    Bril, Reinder J.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Technische Universiteit Eindhoven, Eindhoven, Netherlands.
    A dual shared stack for FSLM in Erika enterprise2017Ingår i: The 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications - WiP Session RTCSA'17, 2017Konferensbidrag (Refereegranskat)
    Abstract [en]

    Recently, the flexible spin-lock model (FSLM) has been introduced, unifying spin-based and suspension-based resource sharing protocols for real-time multi-core platforms. Unlike the multiprocessor stack resource policy (MSRP), FSLM doesn’t allow tasks on a core to share a single stack, however. In this paper, we present a hypothesis claiming that for a restricted range of spin-lock priorities, FSLM requires only two stacks. We briefly describe our implementation of a dual stack for FSLM in the Erika Enterprise RTOS as instantiated on an Altera Nios II platform using 4 soft-core processors.

  • 36.
    Balasubramanian, S.M.N
    et al.
    Tech Univ Eindhoven, Eindhoven, Netherlands.
    Afshar, Sara Zargari
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Gai, Paolo
    Evidence Srl, Pisa, Italy.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    J. Bril, Reinder
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Tech Univ Eindhoven, Eindhoven, Netherlands.
    Incorporating implementation overheads in the analysis for the flexible spin-lock model2017Ingår i: IECON 2017 - 43RD ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, 2017, s. 411-8418Konferensbidrag (Refereegranskat)
    Abstract [en]

    The flexible spin-lock model (FSLM) unifies suspension-based and spin-based resource sharing protocols for partitioned fixed-priority preemptive scheduling based real-time multiprocessor platforms. Recent work has been done in defining the protocol for FSLM and providing a schedulability analysis without accounting for the implementation overheads. In this paper, we extend the analysis for FSLM with implementation overheads. Utilizing an initial implementation of FSLM in the OSEK/VDX-compliant Erika Enterprise RTOS on an Altera Nios II platform using 4 soft-core processors, we present an improved implementation. Given the design of the implementation, the overheads are characterized and incorporated in specific terms of the existing analysis. The paper also supplements the analysis with measurement results, enabling an analytical comparison of FSLM with the natively provided multiprocessor stack resource policy (MSRP), which may serve as a guideline for the choice of FSLM or MSRP for a specific application.

  • 37.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dasari, D.
    Research and Technology Centre, Robert Bosch, India.
    Nelis, V.
    CISTER/INESC-TEC, ISEP, Portugal.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Pinho, L. M.
    CISTER/INESC-TEC, ISEP, Portugal.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Investigation on AUTOSAR-Compliant solutions for many-core architectures2015Ingår i: Proceedings - 18th Euromicro Conference on Digital System Design, DSD 2015, 2015, s. 95-103Konferensbidrag (Refereegranskat)
    Abstract [en]

    As of today, AUTOSAR is the de facto standard in the automotive industry, providing a common software architecture and development process for automotive applications. While this standard is originally written for singlecore operated Electronic Control Units (ECU), new guidelines and recommendations have been added recently to provide support for multicore architectures. This update came as a response to the steady increase of the number and complexity of the software functions embedded in modern vehicles, which call for the computing power of multicore execution environments. In this paper, we enumerate and analyze the design options and the challenges of porting AUTOSAR-based automotive applications onto multicore platforms. In particular, we investigate those options when considering the emerging many-core architectures that provide a more 'scalable' environment than the traditional multicore systems. Such platforms are suitable to enable massive parallel execution, and their design is more suitable for partitioning and isolating the software components.

  • 38.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Analyzing End-to-End Delays in Automotive Systems at Various Levels of Timing Information2016Ingår i: IEEE 4th International Workshop on Real-Time Computing and Distributed systems in Emerging Applications REACTION'16, Porto, Portugal, 2016Konferensbidrag (Refereegranskat)
    Abstract [en]

    Software design for automotive systems is highly complex due to the presence of strict data age constraints for event chains in addition to task specific requirements. These age constraints define the maximum time for the propagation of data through an event chain consisting of independently triggered tasks. Tasks in event chains can have different periods, introducing over- and under-sampling effects, which additionally aggravates their timing analysis. Furthermore, different functionality in these systems, is developed by different suppliers before the final system integration on the ECU. The software itself is developed in a hardware agnostic manner and this uncertainty and limited information at the early design phases may not allow effective analysis of end-to-end delays during that phase. In this paper, we present a method to compute end-to-end delays given the information available in the design phases, thereby enabling timing analysis throughout the development process. The presented methods are evaluated with extensive experiments where the decreasing pessimism with increasing system information is shown.

  • 39.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dasari, Dakshina
    Robert Bosch GmbH, Renningen, Germany.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Analyzing end-to-end delays in automotive systems at various levels of timing information2017Ingår i: ACM SIGBED Review, E-ISSN 1551-3688, Vol. 14, nr 4, s. 8-13Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Software design for automotive systems is highly complex due to the presence of strict data age constraints for event chains in addition to task specific requirements. These age constraints define the maximum time for the propagation of data through an event chain consisting of independently triggered tasks. Tasks in event chains can have different periods, introducing over- and under-sampling effects, which additionally aggravates their timing analysis. Furthermore, different functionality in these systems, is developed by different suppliers before the final system integration on the ECU. The software itself is developed in a hardware agnostic manner and this uncertainty and limited information at the early design phases may not allow effective analysis of end-to-end delays during that phase. In this paper, we present a method to compute end-to-end delays given the information available in the design phases, thereby enabling timing analysis throughout the development process. The presented methods are evaluated with extensive experiments where the decreasing pessimism with increasing system information is shown.

  • 40.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dasari, Dakshina
    Robert Bosch GmbH, Renningen, Germany.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Arcticus Systems AB, Järfälla, Sweden.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    End-to-End Timing Analysis of Cause-Effect Chains in Automotive Embedded Systems2017Ingår i: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 80, nr Supplement C, s. 104-113Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Automotive embedded systems are subjected to stringent timing requirements that need to be verified. One of the most complex timing requirement in these systems is the data age constraint. This constraint is specified on cause- effect chains and restricts the maximum time for the propagation of data through the chain. Tasks in a cause-effect chain can have different activation patterns and different periods, that introduce over- and under-sampling effects, which additionally aggravate the end-to-end timing analysis of the chain. Furthermore, the level of timing information available at various development stages (from modeling of the software architecture to the software implementation) varies a lot, the complete timing information is available only at the implementation stage. This uncertainty and limited timing information can restrict the end-to-end timing analysis of these chains. In this paper, we present methods to compute end-to-end delays based on different levels of system information. The characteristics of different communication semantics are further taken into account, thereby enabling timing analysis throughout the development process of such heterogeneous software systems. The presented methods are evaluated with extensive experiments. As a proof of concept, an industrial case study demonstrates the applicability of the proposed methods following a state-of-the-practice development process.

  • 41.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    MECHAniSer - A Timing Analysis and Synthesis Tool for Multi-Rate Effect Chains with Job-Level Dependencies2016Ingår i: 7th International Workshop on Analysis Tools and Methodologies for Embedded and Real-time Systems WATERS'16, 2016Konferensbidrag (Refereegranskat)
    Abstract [en]

    Many industrial embedded systems have timing con- straints on the data propagation through a chain of independent tasks. These tasks can execute at different periods which leads to under and oversampling of data. In such situations, understand- ing and validating the temporal correctness of end-to-end delays is not trivial. Many industrial areas further face distributed development where different functionalities are integrated on the same platform after the development process. The large effect of scheduling decisions on the end-to-end delays can lead to expensive redesigns of software parts due to the lack of analysis at early design stages. Job-level dependencies is one solution for this challenge and means of scheduling such systems are available. In this paper we present MECHAniSer, a tool targeting the early analysis of end-to-end delays in multi-rate cause effect chains with specified job-level dependencies. The tool further provides the possibility to synthesize job-level dependencies for a set of cause-effect chains in a way such that all end-to-end requirements are met. The usability and applicability of the tool to industrial problems is demonstrated via a case study.

  • 42.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Synthesizing Job-Level Dependencies for Automotive Multi-Rate Effect Chains2016Ingår i: The 22th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'16, 2016, Vol. sept, s. 159-169, artikel-id 579951Konferensbidrag (Refereegranskat)
    Abstract [en]

    Today’s automotive embedded systems comprise a multitude of functionalities, many with complex timing re- quirements. Besides task specific timing requirements, such ap- plications often have timing requirements for the propagation of data through a chain of tasks. An important metric for control applications is the data age, which is addressed in this work. The analysis of such systems is non-trivial because tasks involved in the data propagation may execute at different periods, which leads to over and undersampling within one chain. This work presents a novel method to compute worst- and best-case end-to-end latencies for such systems. A second contribution synthesizes job-level dependencies for such task sets in a way that data paths which exceed the age constraint are eliminated. An extensive evaluation is performed on synthetic task sets and the applicability to industrial applications is demonstrated in a case study.

  • 43.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dasari, Dakshina
    Robert Bosch GmbH, Renningen, Germany.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Timing Analysis and Synthesis of Mixed Multi-Rate Effect Chains in MECHAniSer2016Ingår i: Open Demo Session of Real-Time Systems located at Real Time Systems Symposium (RTSS) RTSS@Work 2016, 2016Konferensbidrag (Refereegranskat)
    Abstract [en]

    The majority of embedded control systems are modeled with several chains of independently triggered tasks, also known as multi-rate effect chains. These chains have often stringent end-to-end timing requirements that should be satisfied before running the system. MECHAniSer is one of the tools that supports end-to-end timing analysis of such chains. In addition, the tool provides the possibility to synthesize job-level dependencies for these chains such that all end-to-end timing requirements are satisfied. In this paper we showcase an extension of MECHAniSer that supports the analysis of mixed chains that contain a mix of independent and dependent tasks.

  • 44.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Nelis, Vincent
    CISTER/INESC-TEC, ISEP, Portugal.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Pinho, Luis Miguel
    CISTER/INESC-TEC, ISEP, Portugal.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Investigation on AUTOSAR-Compliant Solutionsfor Many-Core Architectures2015Ingår i: Proceedings of the 18th Euromicro Conference on Digital System Design (DSD 2015), 2015Konferensbidrag (Refereegranskat)
    Abstract [en]

    As of today, AUTOSAR is the de facto standard inthe automotive industry, providing a common software architectureand development process for automotive applications. Whilethis standard is originally written for singlecore operated ElectronicControl Units (ECU), new guidelines and recommendationshave been added recently to provide support for multicore architectures.This update came as a response to the steady increase ofthe number and complexity of the software functions embedded inmodern vehicles, which call for the computing power of multicoreexecution environments. In this paper, we enumerate and analyzethe design options and the challenges of porting AUTOSAR-basedautomotive applications onto multicore platforms. In particular,we investigate those options when considering the emerging manycorearchitectures that provide a more scalable environment thanthe traditional multicore systems. Such platforms are suitableto enable massive parallel execution, and their design is moresuitable for partitioning and isolating the software components.

  • 45.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Nélis, Vincent
    CISTER/INESC-TEC, ISEP, Portugal.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Partitioning the Network-on-Chip to Enable Virtualization on Many-Core Processors2015Ingår i: The 6th International Real-Time Scheduling Open Problems Seminar RTSOPS'15, 2015Konferensbidrag (Refereegranskat)
    Abstract [en]

    Technological advances have increased the transistor density, thereby ushering in multi- and more recently many-core systems, distinguished by the presence of hundreds of cores on a single chip. For such a platform, the Network-on-Chip (NoC) has emerged as a scalable and efficient interconnect fabric to realize the communication across an ever increasing number of processor cores, memories, and specialized IP blocks both on- and off-chip. In this paper, we highlighted some key problems in NoC based architectures that must be addressed before the deployment of real-time applications onto these platforms becomes possible. A paradigm shift from function centric to data and communication centric approaches is required. Combining hardware and software based flow-regulation seems to be the only way to ensure that NoCs go beyond the best-effort service and address the requirements of diverse applications.

  • 46.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Liu, Meng
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Adaptive Routing of Real-Time Traffic on a 2D-Mesh Based NoC2015Ingår i: The 21st IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, WiP RTCSA-wip'15, 2015Konferensbidrag (Refereegranskat)
  • 47.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Arcticus Systems AB, Järfälla, Sweden.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Extending Automotive Legacy Systems with Existing End-to-End Timing Constraints2018Ingår i: 14th International Conference on Information Technology : New Generations ITNG'17, 2018, Vol. 558, s. 597-605Konferensbidrag (Refereegranskat)
    Abstract [en]

    Developing automotive software is becoming in- creasingly challenging due to continuous increase in its size and complexity. The development challenge is amplified when the industrial requirements dictate extensions to the legacy (previously developed) automotive software while requiring to meet the existing timing requirements. To cope with these challenges, sufficient techniques and tooling to support the modeling and timing analysis of such systems at earlier development phases is needed. Within this context, we focus on the extension of software component chains in the software architectures of automotive legacy systems. Selecting the sampling frequency, i.e. period, for newly added software components is crucial to meet the timing requirements of the chains. The challenges in selecting periods are identified. It is further shown how to automatically assign periods to software components, such that the end-to-end timing requirements are met while the runtime overhead is minimized. An industrial case study is presented that demonstrates the applicability of the proposed solution to industrial problems.

  • 48.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system. Arcticus Systems, Järfälla, Sweden.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    A Generic Framework Facilitating Early Analysis of Data Propagation Delays in Multi-Rate Systems2017Ingår i: The 23th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'17, 2017, artikel-id 8046323Konferensbidrag (Refereegranskat)
    Abstract [en]

    A majority of multi-rate real-time systems are constrained by a multitude of timing requirements, in addition to the traditional deadlines on well-studied response times. This means, the timing predictability of these systems not only depends on the schedulability of certain task sets but also on the timely propagation of data through the chains of tasks from sensors to actuators. In the automotive industry, four different timing constraints corresponding to various data propagation delays are commonly specified on the systems. This paper identifies and addresses the source of pessimism as well as optimism in the calculations for one such delay, namely the reaction delay, in the state-of-the-art analysis that is already implemented in several industrial tools. Furthermore, a generic framework is proposed to compute all the four end-to-end data propagation delays, complying with the established delay semantics, in a scheduler and hardware-agnostic manner. This allows analysis of the system models already at early development phases, where limited system information is present. The paper further introduces mechanisms to generate job-level dependencies, a partial ordering of jobs, which need to be satisfied by any execution platform in order to meet the data propagation timing requirements. The job-level dependencies are first added to all task chains of the system and then reduced to its minimum required set such that the job order is not affected. Moreover, a necessary schedulability test is provided, allowing for varying the number of CPUs. The experimental evaluations demonstrate the tightness in the reaction delay with the proposed framework as compared to the existing state-of-the-art and practice solutions.

  • 49.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Mubeen, Saad
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Scheduling Multi-Rate Real-Time Applications on Clustered Many-Core Architectures with Memory Constraints2018Ingår i: 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2018, s. 560-567Konferensbidrag (Refereegranskat)
    Abstract [en]

    Access to shared memory is one of the main chal- lenges for many-core processors. One group of scheduling strategies for such platforms focuses on the division of tasks’ access to shared memory and code execution. This allows to orchestrate the access to shared local and off-chip memory in a way such that access contention between different compute cores is avoided by design. In this work, an execution framework is introduced that leverages local memory by statically allocating a subset of tasks to cores. This reduces the access times to shared memory, as off-chip memory access is avoided, and in turn improves the schedulability of such systems. A Constrained Programming (CP) formulation is presented to selects the statically allocated tasks and generates the complete system schedule. Evaluations show that the pro- posed approach yields an up to 21% higher schedulability ratio than related work, and a case study demonstrates its applicability to industrial problems.

  • 50.
    Becker, Matthias
    et al.
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nicolic, Borislav
    Technische Universität Braunschweig, Germany.
    Dasari, Dakshina
    Robert Bosch GmbH, Renningen, Germany.
    Åkesson, Benny
    CISTER/INESC-TEC, ISEP, Portugal.
    Nélis, Vincent
    CISTER/INESC-TEC, ISEP, Portugal.
    Behnam, Moris
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Nolte, Thomas
    Mälardalens högskola, Akademin för innovation, design och teknik, Inbyggda system.
    Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform2017Ingår i: 23rd IEEE Real-Time and Embedded Technology and Applications Symposium RTAS'17, 2017, s. 101-112Konferensbidrag (Refereegranskat)
    Abstract [en]

    Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip, which is used for communication among the compute cores via the off- chip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms. In this work, we target a state-of-the-art many-core processor, the Kalray MPPA R . A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis.

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