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  • 1.
    Abdullah, Syed Md Jakaria
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Moghaddami Khalilzad, Nima
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Towards Implementation of Virtual-Clustered Multiprocessor Scheduling in Linux2013In: Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, SIES 2013, 2013, p. 97-100Conference paper (Refereed)
    Abstract [en]

    Cluster based multiprocessor scheduling can be seen as a hybrid approach combining benefits of both partitioned and global scheduling. Virtual clustering further enhances it by providing dynamic cluster resource allocation and applying hierarchical scheduling techniques. Over the years, the study of virtual cluster scheduling has been limited to theoretical analysis. In this paper, we present our initial ideas about implementing virtual cluster scheduling in Linux. The purpose of this implementation is twofold: (i) we would like to demonstrate the feasibility of its implementation in an operating system, without modifying the kernel source code, (ii) we present practical insights on the overhead of implementing this framework.

  • 2.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, R. J.
    Technische Universiteit Eindhoven, Eindhoven, Netherlands .
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Flexible spin-lock model for resource sharing in multiprocessor real-time systems2014In: Proc. IEEE Int. Symp. Ind. Embedded Syst., SIES, 2014, p. 41-51Conference paper (Refereed)
    Abstract [en]

    Various approaches can be utilized upon resource locking for mutually exclusive resource access in multiprocessor platforms. So far two conventional approaches exist for dealing with tasks that are blocked on a global resource in a multi-processor platform. Either the blocked task performs a busy wait, i.e. spins, at the highest priority level until the resource is released, or it is suspended. Although both approaches provide mutually exclusive access to resources, they can introduce long blocking delays to tasks, which may be unacceptable for many industrial applications. In this paper, we propose a general spin-based model for resource sharing in multiprocessor platforms in which the priority of the blocked tasks during spinning can be selected arbitrarily. Moreover, we provide the analysis for two selected spin-lock priorities and we show by means of a general comparison as well as specific examples that these solutions may provide a better performance for higher priority tasks.

  • 3.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, Reinder J.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Resource sharing in a hybrid partitioned/global scheduling framework for multiprocessors2015In: IEEE International Conference on Emerging Technologies and Factory Automation, ETFA, 2015Conference paper (Refereed)
    Abstract [en]

    For resource-constrained embedded real-time systems, resource-efficient approaches are very important. Such an approach is presented in this paper, targeting systems where a critical application is partitioned on a multi-core platform and the remaining capacity on each core is provided to a noncritical application using resource reservation techniques. To exploit the potential parallelism of the non-critical application, global scheduling is used for its constituent tasks. Previously, we enabled intra-application resource sharing for such a framework, i.e. each application has its own dedicated set of resources. In this paper, we enable inter-application resource sharing, in particular between the critical application and the non-critical application. This effectively enables resource sharing in a hybrid partitioned/global scheduling framework on multiprocessors. For resource sharing, we use a spin-based synchronization protocol. We derive blocking bounds and extend existing schedulability analysis for such a system.

  • 4.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, Reinder J.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Technische Universiteit Eindhoven, Eindhoven, Netherlands.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Resource Sharing Under Global Scheduling with Partial Processor Bandwidth2015In: 2015 10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015 - Proceedings, 2015, p. 195-206Conference paper (Refereed)
    Abstract [en]

    Resource efficient approaches are of great importance for resource constrained embedded systems. In this paper, we present an approach targeting systems where tasks of a critical application are partitioned on a multi-core platform and by using resource reservation techniques, the remaining bandwidth capacity on each core is utilized for one or a set of non-critical application(s). To provide a resource efficient solution and to exploit the potential parallelism of the extra applications on the multi-core processor, global scheduling is used to schedule the tasks of the non-critical applications. Recently a specific instantiation of such a system has been studied where tasks do not share resources other than the processor. In this paper, we enable semaphore-based resource sharing among tasks within critical and non-critical applications using a suspension-based synchronization protocol. Tasks of non-critical applications have partial access to the processor bandwidth. The paper provides the systems schedulability analysis where blocking due to resource sharing is bounded. Further, we perform experimental evaluations under balanced and unbalanced allocation of tasks of a critical application to cores.

  • 5.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    J. Bril, Reinder
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Per Processor Spin-Lock Priority for Partitioned Multiprocessor Real-Time Systems2014Report (Other academic)
    Abstract [en]

    Two traditional approaches exist for a task that is blocked on a global resource; a task either performs a non-preemptive busy wait, i.e., spins, or suspends and releases the processor. Previously, we have shown that both approaches can be viewed as spinning either at the highest priority HP or at the lowest priority on the processor LP, respectively. Based on this view, previously we have generalized a task's blocking behavioral model, as spinning at any arbitrary priority level. In this paper, we focus on a particular class of spin-lock protocols from the introduced flexible spin-lock model where spinning is performed at a priority equal to or higher than the highest local ceiling of the global resources accessed on a processor referred to as CP spin-lock approach. In this paper, we assume that all tasks of a specific processor are spinning on the same priority level. Given this class and assumption, we show that there exists a spin-lock protocol in this range that dominates the classic spin-lock protocol which tasks spin on highest priority level (HP). However we show that this new approach is incomparable with the CP spin-lock approach. Moreover, we show that there may exist an intermediate spin-lock approach between the priority used by CP spin-lock approach and the new introduced spin-lock approach that can make a task set schedulable when those two cannot. We provide an extensive evaluation results comparing the HP, CP and the new proposed approach.

  • 6.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    J. Bril, Reinder
    Technische Universiteit Eindhoven, Eindhoven, The Netherlands.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Per Processor Spin-Lock Priority for Partitioned Multiprocessor Real-Time Systems2017In: Leibniz Transactions on Embedded Systems, ISSN 2199-2002, no 2Article in journal (Other academic)
    Abstract [en]

    Two traditional approaches exist for a task that is blocked on a global resource; a task either performs a non-preemptive busy wait, i.e., spins, or suspends and releases the processor. Previously, we have shown that both approaches can be viewed as spinning either at the highest priority HP or at the lowest priority on the processor LP, respectively. Based on this view, previously we have generalized a task's blocking behavioral model, as spinning at any arbitrary priority level. In this paper, we focus on a particular class of spin-lock protocols from the introduced flexible spin-lock model where spinning is performed at a priority equal to or higher than the highest local ceiling of the global resources accessed on a processor referred to as CP spin-lock approach. In this paper, we assume that all tasks of a specific processor are spinning on the same priority level. Given this class and assumption, we show that there exists a spin-lock protocol in this range that dominates the classic spin-lock protocol which tasks spin on highest priority level (HP). However we show that this new approach is incomparable with the CP spin-lock approach. Moreover, we show that there may exist an intermediate spin-lock approach between the priority used by CP spin-lock approach and the new introduced spin-lock approach that can make a task set schedulable when those two cannot. We provide an extensive evaluation results comparing the HP, CP and the new proposed approach.

  • 7.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Integrating independently developed real-time applications on a shared multi-core architecture2013In: ACM SIGBED Review, v. 10, n. 3, 2013, p. 49-56Conference paper (Refereed)
    Abstract [en]

    The shift towards multi-core platforms has become inevitable from an industry perspective, therefore proper techniques are needed to deal with challenges related to this migration from single core architectures to a multi-core architecture. One of the main concerns for the system developers in this context is the migration of legacy real-time systems to multi-core architectures. To address this concern and to simplify migration, independently developed subsystems are abstracted with an interface, such that when working with multiple independently-developed subsystems to be integrated on a shared platform, one does not need to be aware of information or policies used in other subsystems in order to determine subsystem-level schedulability. Instead schedulability can be checked through their interfaces at the time of integration on a shared multi-core architecture. In this paper we propose a solution for the case where some of the independently-developed subsystems are distributed over more than one processor and we propose an approach to generate interfaces of subsystems that may share mutually exclusive resources.

  • 8.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Semi-partitioning under a Blocking-Aware Task Allocation2015In: Proceedings - Real-Time Systems Symposium, 2015, p. 379-379Conference paper (Refereed)
    Abstract [en]

    Semi-partitioned scheduling is a resource efficient scheduling approach compared to the conventional multiprocessor scheduling approaches in terms of system utilization and migration overhead. Semi-partitioned scheduling can better utilize processor bandwidth compared to the partitioned scheduling while introducing less overhead compared to the global scheduling. Various techniques have been proposed to schedule tasks in a semi-partitioned environment, however, they have used blockingagnostic allocation mechanisms in presence of resource sharing protocols. Since, the allocation mechanism can highly affect the system schedulability, in this paper we provide a blocking-aware allocation mechanism for semi-partitioned scheduling framework under a suspension-based resource sharing protocol. We have applied new heuristics for sorting the tasks in the algorithm that shows improvements upon system schedulability. Finally, we present our preliminary results.

  • 9.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Khalilzad, Nima
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, Reinder J.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Universiteit Eindhoven, Eindhoven, Netherlands.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Intra-component Resource Sharing on a Virtual Multiprocessor Platform2016In: ACM SIGBED Review: Special Issue on 8th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems, 2016, p. 31-32Conference paper (Refereed)
    Abstract [en]

    Component-based software development facilitates the development process of large and complex software systems. By the advent of multiprocessors, the independently developed components can be integrated on a multi-core platform to achieve an efficient use of system hardware and a decrease in system power consumption and costs. In this paper, we consider a virtual multiprocessor platform where each component can be dynamically allocated to any set of processors of the platform with a maximum concurrency level. Global-EDF is used for intra-component scheduling. The existing analysis for such systems have assumed that tasks are independent. In this paper, we enable intra-component resource sharing for this platform. We investigate using a spin-based resource sharing protocol with the accompanying analysis that extends the existing analysis for independent tasks. We briefly illustrate and evaluate our initial results with an example.

  • 10.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Moghaddami Khalilzad, Nima
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nemati, Farhang
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Resource Sharing among Prioritized Real-Time Applications on Multiprocessors2015In: ACM SIGBED Review - Special Issue on the 6th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems Homepage archiveVolume 12 Issue 1, 2015, p. 46-55Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a new protocol for handling resource sharing among prioritized real-time applications composed on a multiprocessor platform. We propose an optimal priority assignment algorithm which assigns unique priorities to the applications based on information in their interfaces. We have performed experimental evaluations to compare the proposed protocol (called MSOS-Priority) to the current state of the art locking protocols under multiprocessor partitioned scheduling, i.e., MPCP, MSRP, FMLP, MSOS, and OMLP. The valuations show that MSOS-Priority mostly performs significantly better than alternative approaches.

  • 11.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Nemati, Farhang
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Resource Sharing under Multiprocessor Semi-Partitioned Scheduling2012In: 18th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'12), 2012, p. 290-299Conference paper (Refereed)
    Abstract [en]

    Semi-partitioned scheduling has become the subject of recent interest for multiprocessors due to better utilization results, compared to conventional global and partitioned scheduling algorithms. Under semi-partitioned scheduling, a major group of tasks are assigned to fixed processors while a low number of tasks are allocated to more than one processor. Various task assigning techniques have recently been proposed in a semi-partitioned environment. However, a synchronization mechanism for resource sharing among tasks in semi-partitioned scheduling has not yet been investigated. In this paper we propose and evaluate two methods for handling resource sharing under semi-partitioned scheduling in multiprocessor platforms. The main challenge addressed in this paper is to serve the resource requests of tasks that are assigned to different processors.

  • 12.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Nemati, Farhang
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Towards Resource Sharing under Multiprocessor Semi-Partitioned Scheduling2012In: 7th IEEE International Symposium on Industrial Embedded Systems (SIES'12): Conference Proceedings, 2012, p. 315-318Conference paper (Refereed)
    Abstract [en]

    Semi-partitioned scheduling has been the subject of recent interest, compared with conventional global and partitioned scheduling algorithms for multiprocessors, due to better utilization results. In semi-partitioned scheduling most tasks are assigned to fixed processors while a low number of tasks are split up and allocated to different processors. Various techniques have recently been proposed to assign tasks in a semi-partitioned environment. However, an appropriate resource sharing mechanism for handling the resource requests between tasks in semi-partitioned scheduling has not yet been investigated. In this paper we propose two methods for handling resource sharing under semi-partitioned scheduling in multiprocessor platforms. The main challenge is to handle the resource requests of tasks that are split over multiple processors.

  • 13.
    Afshar, Sara Zargari
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    J. Bril, Reinder
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Technische Universiteit Eindhoven, Eindhoven, Netherlands.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    An optimal spin-lock priority assignment algorithm for real-time multi-core systems2017In: The 23th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'17, 2017, article id 8046310Conference paper (Refereed)
    Abstract [en]

    Support for exclusive access to shared (global) resources is instrumental in the context of embedded real-time multi-core systems, and mechanisms for achieving such access must be deterministic and efficient. There exist two traditional approaches for multiprocessors when a task requests a global resource that is locked by a task on a remote core: a spin-based approach, i.e. non-preemptive busy waiting for the resource to become available, and a suspension-based approach, i.e. the task relinquishes the processor. A suspension-based approach can be viewed as a spin-based approach where the lowest priority on a core is used during spinning, similar to a non-preemptive spin-based approach where the highest priority on a core is used. By taking such a view, we previously provided a general model for spinning, where any arbitrary priority can be used for spinning, i.e. from the lowest to the highest priority on a core. Targeting partitioned fixed-priority preemptive scheduled multiprocessors and spin-based approaches that use a fixed priority for spinning per core for all tasks, we aim at increasing the schedulability of multiprocessor systems by using the spin-lock priority per core as parameter. In this paper, we present (i) a generalization of the traditional worst-case response-time analysis for non-preemptive spin-based approaches addressing an arbitrary but fixed spin-lock priority per core, (ii) an optimal spin-lock priority assignment (OSPA) algorithm per core, i.e. an algorithm that will find a fixed spin-lock priority per core that will make the system schedulable, whenever such an assignment exists and, (iii) comparative evaluations of the OSPA algorithm with the spin-based and suspension-based approaches where OSPA showed up to 38% improvement compared to both approaches.

  • 14.
    Al-Dulaimy, Auday
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Dalarna University, Falun, Sweden.
    Ashjaei, Seyed Mohammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Papadopoulos, Alessandro
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Fault Tolerance in Cloud Manufacturing: An Overview2023In: Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, LNICST, vol 495, Springer Science and Business Media Deutschland GmbH , 2023, p. 89-101Conference paper (Refereed)
    Abstract [en]

    Utilizing edge and cloud computing to empower the profitability of manufacturing is drastically increasing in modern industries. As a result of that, several challenges have raised over the years that essentially require urgent attention. Among these, coping with different faults in edge and cloud computing and recovering from permanent and temporary faults became prominent issues to be solved. In this paper, we focus on the challenges of applying fault tolerance techniques on edge and cloud computing in the context of manufacturing and we investigate the current state of the proposed approaches by categorizing them into several groups. Moreover, we identify critical gaps in the research domain as open research directions. 

  • 15.
    Al-Dulaimy, Auday
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Taheri, J.
    Karlstad University, Karlstad, Sweden.
    Papadopoulos, Alessandro
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    LOOPS: A Holistic Control Approach for Resource Management in Cloud Computing2021In: ICPE 2021 - Proceedings of the ACM/SPEC International Conference on Performance Engineering, Association for Computing Machinery, Inc , 2021, p. 117-124Conference paper (Refereed)
    Abstract [en]

    In cloud computing model, resource sharing introduces major benefits for improving resource utilization and total cost of ownership, but it can create technical challenges on the running performance. In practice, orchestrators are required to allocate sufficient physical resources to each Virtual Machine (VM) to meet a set of predefined performance goals. To ensure a specific service level objective, the orchestrator needs to be equipped with a dynamic tool for assigning computing resources to each VM, based on the run-Time state of the target environment. To this end, we present LOOPS, a multi-loop control approach, to allocate resources to VMs based on the service level agreement (SLA) requirements and the run-Time conditions. LOOPS is mainly composed of one essential unit to monitor VMs, and three control levels to allocate resources to VMs based on requests from the essential node. A tailor-made controller is proposed with each level to regulate contention among collocated VMs, to reallocate resources if required, and to migrate VMs from one host to another. The three levels work together to meet the required SLA. The experimental results have shown that the proposed approach can meet applications' performance goals by assigning the resources required by cloud-based applications. 

  • 16.
    Alhashimi, Anas
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. University of Baghdad, Baghdad, Iraq.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Papadopoulos, Alessandro
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Change-Point and Model Estimation with Heteroskedastic Noise and Unknown Model Structure2023In: Int. Conf. Control, Decis. Inf. Technol., CoDIT, Institute of Electrical and Electronics Engineers Inc. , 2023, p. 2126-2132Conference paper (Refereed)
    Abstract [en]

    In this paper, we investigate the problem of modeling time-series as a process generated through (i) switching between several independent sub-models; (ii) where each sub-model has heteroskedastic noise, and (iii) a polynomial bias, describing nonlinear dependency on system input. First, we propose a generic nonlinear and heteroskedastic statistical model for the process. Then, we design Maximum Likelihood (ML) parameters estimation method capable of handling heteroscedasticity and exploiting constraints on model structure. We investigate solving the intractable ML optimization using population-based stochastic numerical methods. We then find possible model change-points that maximize the likelihood without over-fitting measurement noise. Finally, we verify the usefulness of the proposed technique in a practically relevant case study, the execution-time of odometry estimation for a robot operating radar sensor, and evaluate the different proposed procedures using both simulations and field data.

  • 17.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, Luis
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    MTU Assignment in a Master-Slave Switched Ethernet Network2013Conference paper (Refereed)
    Abstract [en]

    In this paper, we investigate the problem of selecting the Maximal Transmission Unit (MTU) size that maximizes the schedulability of real-time messages. We focus on a bandwidth-efficient master-slave switched Ethernet protocol, namely the FTT-SE protocol. We propose an algorithm to find the MTU for each message in order to maximize the schedulability of the messages. Moreover, we evaluate our proposed algorithm and we show that setting the MTU for messages using the algorithm increases the schedulability of messages compared with assigning the MTU to the maximum value that the protocol can support.

  • 18.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, Luis
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. University of Porto, Porto, Portugal .
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    MTU Configuration for Real-Time Switched Ethernet Networks2016In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 70, p. 15-25Article in journal (Refereed)
    Abstract [en]

    In this paper, we show that in real-time switched Ethernet networks reducing the Maximum Transmission Unit (MTU) size may cause an increase or decrease in the response time of messages. This contradicting behavior arises an optimization problem for configuring the MTU size. We formulate the optimization problem in the context of the multi-hop HaRTES architecture, which is a hard real-time Ethernet protocol. As part of the solution, we propose a search-based algorithm to achieve optimum solutions. We modify the algorithm by presenting two techniques to reduce the search space. Then, we propose a heuristic algorithm with a pseudo-polynomial time complexity based on the search-based algorithm. We perform several experiments, and we show that the proposed heuristic results in an improvement regarding messages response times, compared with configuring the MTU to the maximum or minimum values. Moreover, we show in small network configurations that the heuristic performs as good as the search-based algorithm in many cases.

  • 19.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, Luis
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Performance Analysis of Master-Slave Multi-Hop Switched Ethernet Networks2013In: Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, SIES 2013, 2013, p. 280-289Conference paper (Refereed)
    Abstract [en]

    There is an increasing trend towards using switched Ethernet in real-time distributed systems due to features like absence of collisions and high throughput. Nevertheless, a few problems persist, in particular related to priority inversion and limited length in queues. In this paper we focus on a protocol which uses a master-slave technique over standard switched Ethernet in order to overcome such problems, namely FTT-SE protocol. We present an improved response time analysis for such a network and we compare, analytically and with simulations, the results achieved with Network Calculus on a worst-case scenario. We show that our proposed response time analysis gives tighter bounds compared to Network Calculus. Moreover, we compare the performance of different solutions to scale the FTT-SE protocol with respect to the bandwidth utilization. Finally, we propose a new architecture to improve the average performance of master-slave switched Ethernet networks.

  • 20.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Malardalen Univ, Malardalen Real Time Res Ctr MRTC, POB 883, SE-72123 Vasteras, Sweden..
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Malardalen Univ, Malardalen Real Time Res Ctr MRTC, POB 883, SE-72123 Vasteras, Sweden..
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Malardalen Univ, Malardalen Real Time Res Ctr MRTC, POB 883, SE-72123 Vasteras, Sweden..
    SEtSim: A modular simulation tool for switched Ethernet networks2016In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 65, p. 1-14Article in journal (Refereed)
    Abstract [en]

    Using high bandwidth network technologies in real-time applications, for example in automotive systems, is rapidly increasing. In this context, switched Ethernet-based protocols are becoming more popular due to their features such as providing a collision-free domain for transmission of messages. Moreover, switched Ethernet is a mature technology. Several protocols based on switched Ethernet have been proposed over the years, tuned for time critical applications. However, research for improving the features and performance of these protocols is still on-going. In order to evaluate the performance of early stage proposed protocols, the mathematical analysis and/or experiments are required. However, performing an experiment for complex network topologies with a large set of messages is not effortless. Therefore, using a simulation based approach for evaluating a protocol's performance and/or properties is highly useful. As a response to this we have developed a simulator, called SEtSim, for switched Ethernet networks. SEtSim is developed based on Simulink, and it currently supports different network topologies of the FIT-SE protocol as well as Ethernet AVB protocol. However, the kernel of SEtSim is designed such that it is possible to add and integrate other switched Ethernet-based protocols. In this paper, we describe the design of SEtSim and we show its scalability.

  • 21.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering. Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering. Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering. Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    SEtSim: A Modular Simulation Tool for Switched Ethernet Networks2014Report (Other academic)
    Abstract [en]

    Using high bandwidth network technologies in real-time applications, for example in automotive systems, is rapidly increasing. In this context, switched Ethernet-based protocols are becoming more popular due to their features such as providing a collision-free domain for transmission of messages. Moreover, switched Ethernet is a mature technology. Several protocols based on switched Ethernet have been proposed over the years, tuned for time critical applications. However, research for improving the features and performance of these protocols is still on-going. In order to evaluate the performance of early stage proposed protocols, the mathematical analysis and/or experiments are required. However, performing an experiment for complex network topologies with a large set of messages is not effortless. Therefore, using a simulation based approach for evaluating a protocol's performance and/or properties is highly useful. As a response to this we have, based on Simulink, developed a simulator, called SEtSim, for switched Ethernet networks. SEtSim currently supports different network topologies of the FTT-SE protocol, a master-slave protocol designed for standard Ethernet switches, as well as Ethernet AVB protocol. However, the kernel of SEtSim is designed such that it is possible to add and integrate other switched Ethernet-based protocols. In this paper, we describe the design of SEtSim and we show its scalability.

  • 22.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    The Design and Implementation of a Simulator for Switched Ethernet Networks2012In: 3rd International Workshop on Analysis Tools andMethodologies for Embeddedand Real-time Systems / [ed] Tommaso Cucinotta and Giuseppe Lipari, 2012, p. 57-62Conference paper (Refereed)
    Abstract [en]

    In the context of Switched Ethernet, the Flexible Time-Triggered Switched Ethernet protocol (FTT-SE) was proposed to overcome the limitations and related problems of using COTS switches in real-time networks, such as overflow of switch queues due to uncontrolled arrival of packets. Although the FTT-SE protocol has been validated by several experiments on real applications, evaluation of different architectures as well as evaluation of large scale networks is not straightforward. Therefore, a simulator to evaluate different network architectures based on the FTT-SE protocol is useful. In this paper we present such a simulator. We address the extended FTT-SE protocol using multiple switches and we present a modular simulator based on Simulink/Matlab to visualize message transmissions and to evaluate end-to-end delay bounds of messages.

  • 23.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Almeida, Luis
    University of Porto.
    Marau, Ricardo
    University of Porto.
    A Compact Approach to Clustered Master-Slave Ethernet Networks2012In: IEEE International Workshop on Factory Communication Systems - Proceedings, WFCS, 2012, p. 157-160Conference paper (Refereed)
    Abstract [en]

    Ethernet switches are increasingly used in real-time distributed systems as a technical solution to guarantee the timeliness in communications. However, there are still limitations related to real-time behavior caused by the limited number of priority levels and the possibility of memory overruns with consequent message losses. These limitations can be eliminated using a master/slave technique such as proposed by the FTT paradigm. This led to the FTT-SE protocol that schedules transmissions centrally in a master node. While this protocol has already been well studied and investigated for small networks with a single switch, its extension to larger networks is still an open issue. In this paper we propose a compact clustered solution to scale the FTT-SE protocol to networks of multiple switches by organizing the network in sub-networks composed of one master and one switch each and which can be connected directly, without bridges. This paper also shows how the timeliness of the traffic can still be enforced. The validation is currently on-going.

  • 24.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Pedreiras, Paulo
    University of Aveiro, Portugal.
    Bril, Reinder J.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, Luis
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Reduced Buffering Solution for Multi-Hop HaRTES Switched Ethernet Networks2014In: The 20th IEEE International Conference on embedded and Real-Time Computing Systems and Applications RTCSA'14, 2014, p. Article number 6910504-Conference paper (Refereed)
    Abstract [en]

    In the context of switched Ethernet networks, multi-hop communication is essential as the networks in industrial applications comprise a high amount of nodes, that is far beyond the capability of a single switch. In this paper, we focus on multi-hop communication using HaRTES switches. The HaRTES switch is a modified Ethernet switch that provides real-time traffic scheduling, dynamic Quality-of-Service and temporal isolation between real-time and non-real-time traffic. Herein, we propose a method, called Reduced Buffering Scheme, to conduct the traffic through multiple HaRTES switches in a multi-hop HaRTES architecture. In order to enable the new scheduling method we propose to modify the HaRTES switch structure. Moreover, we develop a response time analysis for the new method. We also compare the proposed method with a method previously proposed, called Distributed Global Scheduling, based on their traffic response times. We show that, the new method forwards all types of traffic including the highest, the medium and the lowest priority, faster than the previous method in most of the cases. Furthermore, we show that the new method performs even better for larger networks compared with the previous one.

  • 25.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Rodriguez-Navas, Guillermo
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Universitat de les Illes Balears, Spain.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Implementing a Clock Synchronization Protocol on a Multi-Master Switched Ethernet Network2013Conference paper (Refereed)
    Abstract [en]

    The interest to use Switched Ethernet technologies in real-time communication is increasing due to its absence of collisions when transmitting messages. Nevertheless, using COTS switches affect the timeliness guarantee inherent in potentially overflowing internal FIFO queues. In this paper we focus on a solution, called the FTT-SE protocol, which is developed based on a master-slave technique. Recently, an extension of the FTT-SE protocol has been proposed where the transmission of messages are controlled using multiple master nodes. In order to guarantee the correctness of the protocol, the masters should be timely synchronized. Therefore, in this paper we investigate using a clock synchronization protocol, based on the IEEE 1588 standard, among master nodes and we study the effects of this protocol on the network performance. In addition, we present a formal verification of this solution by means of model checking to prove the correctness of the FTT-SE protocol when the clock synchronization protocol is applied.

  • 26.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Du, Yong
    Almeida, L.
    University of Porto, Porto, Portugal .
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dynamic reconfiguration in HaRTES switched ethernet networks2016In: IEEE International Workshop on Factory Communication Systems - Proceedings, WFCS, 2016, article id Article number 7496510Conference paper (Refereed)
    Abstract [en]

    The ability of reconfiguring a system during runtime is essential for dynamic real-time applications in which resource usage is traded online for quality of service. The HaRTES switch, which is a modified Ethernet switch, holds this ability for the network resource, and at the same time it provides hard real-time support for both periodic and sporadic traffic. Although the HaRTES switch technologically caters this ability, a protocol to actually perform the dynamic reconfiguration is missing in multi-hop HaRTES networks. In this paper we introduce such a protocol that is compatible with the traffic scheduling method used in the architecture. We prove the correctness of the protocol using a model checking technique. Moreover, we conduct a set of simulation experiments to show the performance of the protocol and we also show that the reconfiguration process is terminated within a bounded time. 

  • 27.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Khalilzad, Nima
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. IS (Embedded Systems).
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sander, Ingo
    Royal Institute of Technology, Sweden.
    Almeida, Luis
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Designing End-to-end Resource Reservations in Predictable Distributed Embedded Systems2017In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 53, no 6, p. 916-956Article in journal (Refereed)
    Abstract [en]

    Contemporary distributed embedded systems in many domains have become highly complex due to ever-increasing demand on advanced computer controlled functionality. The resource reservation techniques can be effective in lowering the software complexity, ensuring predictability and allowing flexibility during the development and execution of these systems. This paper proposes a novel end-to-end resource reservation model for distributed embedded systems. In order to support the development of predictable systems using the proposed model, the paper provides a method to design resource reservations and an end-to-end timing analysis. The reservation design can be subjected to different optimization criteria with respect to runtime footprint, overhead or performance. The paper also presents and evaluates a case study to show the usability of the proposed model, reservation design method and end-to-end timing analysis. 

  • 28.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Liu, Meng
    Mälardalen University, School of Innovation, Design and Engineering.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Mifdaoui, A.
    University of Toulouse, France.
    Almeida, L.
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Worst-case delay analysis of master-slave switched ethernet networks2012In: Proceeings of the 2nd International Workshop on Worst-Case Traversal Time: Proceeding, 2012, p. 15-21Conference paper (Refereed)
    Abstract [en]

    Switched Ethernet is increasingly used in real-time communication due to its intrinsic features such as micro segmentation and high throughput. However, COTS switches may impose long blocking times due to their FIFO queues and can also experience buffer overflow in outgoing queues due to uncontrolled packets arrival. The FTT-SE protocol uses a Master-Slave technique to overcome the COTS switch limitations in real-time applications. Recently, we extended the protocol for large scale networks and in this paper we present the worst-case delay analysis using the Network Calculus formalism for such a network. Moreover, we assess the end-to-end delay of traffic with simulation concluding that the obtained analytical results present a good match with the observed delays, providing uppers bounds that vary between 0% and 50% above the maximum measured values. © 2012 ACM.

  • 29.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, Luis
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    End-to-end Resource Reservations in Distributed Embedded Systems2016In: Proceedings - 2016 IEEE 22nd International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2016, 2016, p. 1-11, article id 7579921Conference paper (Refereed)
    Abstract [en]

    The resource reservation techniques provide effective means to lower the software complexity, ensure predictability and allow flexibility during the development and execution of complex distributed embedded systems. In this paper we propose a new end-to-end resource reservation model for distributed embedded systems. The model is comprehensive in such a way that it supports end-to-end resource reservations on distributed transactions with various activation patterns that are commonly used in industrial control systems. The model allows resource reservations on processors and real-time network protocols. We also present timing analysis for the distributed embedded systems that are developed using the proposed model. The timing analysis computes the end-to-end response times as well as delays such as data age and reaction delays. The presented analysis also supports real-time networks that can autonomously initiate transmissions. Such networks are not supported by the existing analyses. We also include a case study to show the usability of the model and end-to-end timing analysis with resource reservations.

  • 30.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    End-to-end Resource Reservation Model2016Manuscript (preprint) (Other academic)
  • 31.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Patti, Gaetano
    University of Catania, Italy.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Alderisi, Giuliana
    University of Catania, Italy.
    Lo Bello, Lucia
    University of Catania, Italy.
    Schedulability Analysis of Ethernet Audio Video Bridging Networks with Scheduled Traffic Support2017In: Real-time systems, ISSN 0922-6443, E-ISSN 1573-1383, Vol. 53, no 4, p. 526-577Article in journal (Refereed)
    Abstract [en]

    The IEEE Audio Video Bridging (AVB) technology is nowadays under consideration in several automation domains, such as, automotive, avionics, and industrial communications. AVB offers several benefits, such as open specifications, the existence of multiple providers of electronic components, and the real-time support, as AVB provides bounded latency to real-time traffic classes. In addition to the above mentioned properties, in the automotive domain, comparing with the existing in-vehicle networks, AVB offers significant advantages in terms of high bandwidth, significant reduction of cabling costs, thickness and weight, while meeting the challenging EMC/EMI requirements. Recently, an improvement of the AVB protocol, called the AVB ST, was proposed in the literature, which allows for supporting scheduled traffic, i.e., a class of time-sensitive traffic that requires time-driven transmission and low latency. In this paper, we present a schedulability analysis for the real-time traffic crossing through the AVB ST network. In addition, we formally prove that, if the bandwidth in the network is allocated according to the AVB standard, the schedulability test based on response time analysis will fail for most cases even if, in reality, these cases are schedulable. In order to provide guarantees based on analysis test a bandwidth over-reservation is required. In this paper, we propose a solution to obtain a minimized bandwidth over-reservation. To the best of our knowledge, this is the first attempt to formally spot the limitation and to propose a solution for overcoming it. The proposed analysis is applied to both the AVB standard and the AVB ST. The analysis results are compared with the results of several simulative assessments, obtained using OMNeT++, on both automotive and industrial case studies. The comparison between the results of the analysis and the simulation ones shows the effectiveness of the analysis proposed in this work.

  • 32.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Pedreiras, P.
    University of Aveiro, Aveiro, Portugal .
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, L.
    University of Porto, Porto, Portugal.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Evaluation of dynamic reconfiguration architecture in multi-hop switched ethernet networks2014In: 19th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2014, 2014, p. Article number 7005322-Conference paper (Refereed)
    Abstract [en]

    On-the-fly adaptability and reconfigurability are recently becoming an interest in real-time communications. To assure a continued real-time behavior, the admission control with a quality-of-service mechanism is required, that screen all adaptation and reconfiguration requests. In the context of switched Ethernet networks, the FTT-SE protocol provides adaptive real-time communication. Recently, we proposed two methods to perform the online reconfiguration in multi-hop FTT-SE architectures. However, the methods lack the experimental evaluation. In this paper, we evaluate both methods in terms of the reconfiguration time. 

  • 33.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Pedreiras, P.
    DETI/IT, University of Aveiro, Aveiro, Portugal .
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, Reinder J.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Technische Universiteit Eindhoven (TU/e), Netherlands .
    Almeida, L.
    Technische Universiteit Eindhoven (TU/e), Netherlands .
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Response time analysis of multi-hop HaRTES Ethernet Switch networks2014In: IEEE Int. Workshop Factory Commun. Syst. Proc. WFCS, 2014Conference paper (Refereed)
    Abstract [en]

    In this paper we focus on micro-segmented switched-Ethernet networks with HaRTES switches. HaRTES switches provide synchronous and asynchronous real-time traffic scheduling, dynamic Quality-of-Service adaptation and transparent integration of real-time and non-real-time nodes. Herein we investigate the challenges of connecting multiple HaRTES switches in order to build multi-hop communication and we propose a method, named Distributed Global Scheduling, to handle the traffic forwarding in such an architecture while preserving the unique properties of the single HaRTES switch case. Moreover, we develop a response time analysis for the method. We also evaluate the level of pessimism embodied in the anal-ysis. Finally, we show the applicability of the proposed method in an industrial setting by applying it in an automotive case study.

  • 34.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Pedreiras, Paulo
    University of Aveiro, Portugal.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, Luis
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dynamic Reconfiguration in Multi-Hop Switched Ethernet Networks2014In: ACM SIGBED Review. Special Issue on 6th Workshop on Adaptive and Reconfigurable Embedded Systems (APRES 2014), ISSN 1551-3688, Vol. 11, no 3, p. 62-65Article in journal (Refereed)
    Abstract [en]

    The FTT-SE protocol provides adaptive real-time communication on Ethernet networks. To assure a continued real-time behavior, FTT-SE integrates admission control with a quality-of-service mechanism, which screen all adaptation and reconfiguration requests, accepting only those that do not compromise the system timeliness. The adaptability and reconfigurability have been deeply studied in the case of single switch FTT-SE architectures, whereas the extension of that for the multi-hop FTT-SE architecture was not yet investigated. Therefore, in this paper we study the challenges of enabling dynamic reconfiguration in multi-hop FTT-SE networks, we propose two methods (one centralized and one distributed) and we present a qualitative comparison between them.

  • 35.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Pedreiras, Paulo
    University of Aveiro, Portugal.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, Luis
    University of Porto, Portugal.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Supporting Multi-Hop Communications with HaRTES Ethernet Switches2013Conference paper (Refereed)
    Abstract [en]

    In this paper we identify the challenges of multi-hop communication when using a micro-segmented switched-Ethernet protocol with enhanced HaRTES switches. The HaRTES architecture has been explored in the scope of single-switch topology, and provides dynamic virtual channels that can be composed hierarchically and provide bounded latency together with temporal isolation. Herein we propose two different solutions regarding the traffic forwarding in multi-switch architectures, while maintaining the unique properties of the single HaRTES switch case. In the first approach, the traffic is buffered and scheduled sequentially in each hop. In the second solution the traffic is scheduled once and forwarded immediately through multiple switches without buffering. In this paper we present a brief comparison of both approaches and we report on the on-going work towards effective support to real-time communications in dynamic and complex Cyber-Physical Systems.

  • 36.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. MRTC Malardalen Univ, Vasteras, Sweden..
    Silva, Luis
    DETI IT Univ Aveiro, Aveiro, Portugal..
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. MRTC Malardalen Univ, Vasteras, Sweden..
    Pedreiras, Paulo
    DETI IT Univ Aveiro, Aveiro, Portugal..
    Bril, Reinder J.
    Tech Univ Eindhoven TU E, Eindhoven, Netherlands..
    Almeida, Luis
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. MRTC Malardalen Univ, Vasteras, Sweden.;IT DEEC Univ Porto, Oporto, Portugal..
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. MRTC Malardalen Univ, Vasteras, Sweden..
    Improved Message Forwarding for Multi-Hop HaRTES Real-Time Ethernet Networks2016In: Journal of Signal Processing Systems, ISSN 1939-8018, E-ISSN 1939-8115, Vol. 84, no 1, p. 47-67Article in journal (Refereed)
    Abstract [en]

    Nowadays, switched Ethernet networks are used in complex systems that encompass tens to hundreds of nodes and thousands of signals. Such scenarios require multi-switch architectures where communications frequently occur in multiple hops. In this paper we investigate techniques to allow efficient multi-hop communication using HaRTES switches. These are modified Ethernet switches that provide real-time traffic scheduling, dynamic bandwidth management and temporal isolation between real-time and non-real-time traffic. This paper addresses the problem of forwarding traffic in HaRTES networks. Two methods have been recently proposed, namely Distributed Global Scheduling (DGS) that buffers traffic between switches, and Reduced Buffering Scheme (RBS), that uses immediate forwarding. In this paper, we discuss the design and implementation of RBS within HaRTES and we carry out an experimental validation with a prototype implementation. Then, we carry out a comparison between RBS and DGS using worst-case response time analysis and simulation. The comparison clearly establishes the superiority of RBS concerning end-to-end response times. In fact, with sample message sets, we achieved reductions in end-to-end delay that were as high as 80 %.

  • 37.
    Ashjaei, Seyed Mohammad Hossein
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lundbäck, John
    Arcticus Systems AB, Sweden.
    Gålnander, Mattias
    Arcticus Systems AB, Sweden.
    Lundbäck, Kurt-Lennart
    Arcticus Systems AB, Sweden.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Modeling and Timing Analysis of Vehicle Functions Distributed over Switched Ethernet2017In: IECON 2017 - 43RD ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, 2017, p. 8419-8424Conference paper (Refereed)
    Abstract [en]

    This paper proposes an approach to model switched Ethernet communication within a model- and component-based software development framework for vehicular distributed embedded systems. The paper also presents a method to extract the network timing model from the systems that use switched Ethernet networks. In order to provide a proof of concept, an existing industrial component model and its tool suite, namely RCM and Rubus-ICE respectively, are extended by implementing the modeling technique, the timing model extraction method and response-time analysis of the Ethernet AVB protocol. The extensions to RCM are backward compatible with the modeling and end-to-end timing analysis of traditional in-vehicle networks and legacy (previously developed) vehicular distributed embedded systems. Furthermore, the paper discusses the implementation and test strategy used in this work. Finally, the usability of the modeling approach and implemented timing analysis is demonstrated by modeling and time analyzing a vehicular application case study with the extended component model and tool suite.

  • 38.
    Bassi, Ezio
    et al.
    University of Pavia, Italy.
    Benzi, Francesco
    University of Pavia, Italy.
    Facchinetti, Tullio
    Almeida, Luis
    University of Porto.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Powerline Communication in Electric Vehicles2009In: IEEE International Electric Machines and Drives Conference (IEMDC'09), 2009, p. 1749-1753Conference paper (Refereed)
    Abstract [en]

    In full electric (EV) or hybrid electric (HEV) vehicles the onboard communication is a crucial issue, that can take advantage from a reliable and robust interaction among the embedded units (ECUs) providing among others the power and batteries management, services, accessories and supervision; an updated global view of the system under control (the car) can improve the quality of control, reliability, safety and comfort. Power Line Communication technology (PLC), that take advantage of the DC power line as a physical medium to exchange messages, according to standard protocols, is a candidate at substituting the actual wired solutions, by substantially reducing the cabling burden. The present paper aims at i) reviewing PLC technology for DC bus in the automotive sector; ii) defining the requirements of a reliable communication systems within a car environment, with special attention given to the data exchange needed by the more critical systems in EV and HEV, and namely the control of electrical actuators for traction; iii) describing a benchmark for testing the data transfer characteristics and performance, including details on proposed protocols and architectures and presenting experimental results on data channel characterization and transmission.

  • 39.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, D.
    Research and Technology Centre, Robert Bosch, India.
    Nelis, V.
    CISTER/INESC-TEC, ISEP, Portugal.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Pinho, L. M.
    CISTER/INESC-TEC, ISEP, Portugal.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Investigation on AUTOSAR-Compliant solutions for many-core architectures2015In: Proceedings - 18th Euromicro Conference on Digital System Design, DSD 2015, 2015, p. 95-103Conference paper (Refereed)
    Abstract [en]

    As of today, AUTOSAR is the de facto standard in the automotive industry, providing a common software architecture and development process for automotive applications. While this standard is originally written for singlecore operated Electronic Control Units (ECU), new guidelines and recommendations have been added recently to provide support for multicore architectures. This update came as a response to the steady increase of the number and complexity of the software functions embedded in modern vehicles, which call for the computing power of multicore execution environments. In this paper, we enumerate and analyze the design options and the challenges of porting AUTOSAR-based automotive applications onto multicore platforms. In particular, we investigate those options when considering the emerging many-core architectures that provide a more 'scalable' environment than the traditional multicore systems. Such platforms are suitable to enable massive parallel execution, and their design is more suitable for partitioning and isolating the software components.

  • 40.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Analyzing End-to-End Delays in Automotive Systems at Various Levels of Timing Information2016In: IEEE 4th International Workshop on Real-Time Computing and Distributed systems in Emerging Applications REACTION'16, Porto, Portugal, 2016Conference paper (Refereed)
    Abstract [en]

    Software design for automotive systems is highly complex due to the presence of strict data age constraints for event chains in addition to task specific requirements. These age constraints define the maximum time for the propagation of data through an event chain consisting of independently triggered tasks. Tasks in event chains can have different periods, introducing over- and under-sampling effects, which additionally aggravates their timing analysis. Furthermore, different functionality in these systems, is developed by different suppliers before the final system integration on the ECU. The software itself is developed in a hardware agnostic manner and this uncertainty and limited information at the early design phases may not allow effective analysis of end-to-end delays during that phase. In this paper, we present a method to compute end-to-end delays given the information available in the design phases, thereby enabling timing analysis throughout the development process. The presented methods are evaluated with extensive experiments where the decreasing pessimism with increasing system information is shown.

  • 41.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Robert Bosch GmbH, Renningen, Germany.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Analyzing end-to-end delays in automotive systems at various levels of timing information2017In: ACM SIGBED Review, E-ISSN 1551-3688, Vol. 14, no 4, p. 8-13Article in journal (Refereed)
    Abstract [en]

    Software design for automotive systems is highly complex due to the presence of strict data age constraints for event chains in addition to task specific requirements. These age constraints define the maximum time for the propagation of data through an event chain consisting of independently triggered tasks. Tasks in event chains can have different periods, introducing over- and under-sampling effects, which additionally aggravates their timing analysis. Furthermore, different functionality in these systems, is developed by different suppliers before the final system integration on the ECU. The software itself is developed in a hardware agnostic manner and this uncertainty and limited information at the early design phases may not allow effective analysis of end-to-end delays during that phase. In this paper, we present a method to compute end-to-end delays given the information available in the design phases, thereby enabling timing analysis throughout the development process. The presented methods are evaluated with extensive experiments where the decreasing pessimism with increasing system information is shown.

  • 42.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Robert Bosch GmbH, Renningen, Germany.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Arcticus Systems AB, Järfälla, Sweden.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    End-to-End Timing Analysis of Cause-Effect Chains in Automotive Embedded Systems2017In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 80, no Supplement C, p. 104-113Article in journal (Refereed)
    Abstract [en]

    Automotive embedded systems are subjected to stringent timing requirements that need to be verified. One of the most complex timing requirement in these systems is the data age constraint. This constraint is specified on cause- effect chains and restricts the maximum time for the propagation of data through the chain. Tasks in a cause-effect chain can have different activation patterns and different periods, that introduce over- and under-sampling effects, which additionally aggravate the end-to-end timing analysis of the chain. Furthermore, the level of timing information available at various development stages (from modeling of the software architecture to the software implementation) varies a lot, the complete timing information is available only at the implementation stage. This uncertainty and limited timing information can restrict the end-to-end timing analysis of these chains. In this paper, we present methods to compute end-to-end delays based on different levels of system information. The characteristics of different communication semantics are further taken into account, thereby enabling timing analysis throughout the development process of such heterogeneous software systems. The presented methods are evaluated with extensive experiments. As a proof of concept, an industrial case study demonstrates the applicability of the proposed methods following a state-of-the-practice development process.

  • 43.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    MECHAniSer - A Timing Analysis and Synthesis Tool for Multi-Rate Effect Chains with Job-Level Dependencies2016In: 7th International Workshop on Analysis Tools and Methodologies for Embedded and Real-time Systems WATERS'16, 2016Conference paper (Refereed)
    Abstract [en]

    Many industrial embedded systems have timing con- straints on the data propagation through a chain of independent tasks. These tasks can execute at different periods which leads to under and oversampling of data. In such situations, understand- ing and validating the temporal correctness of end-to-end delays is not trivial. Many industrial areas further face distributed development where different functionalities are integrated on the same platform after the development process. The large effect of scheduling decisions on the end-to-end delays can lead to expensive redesigns of software parts due to the lack of analysis at early design stages. Job-level dependencies is one solution for this challenge and means of scheduling such systems are available. In this paper we present MECHAniSer, a tool targeting the early analysis of end-to-end delays in multi-rate cause effect chains with specified job-level dependencies. The tool further provides the possibility to synthesize job-level dependencies for a set of cause-effect chains in a way such that all end-to-end requirements are met. The usability and applicability of the tool to industrial problems is demonstrated via a case study.

  • 44.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Synthesizing Job-Level Dependencies for Automotive Multi-Rate Effect Chains2016In: The 22th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'16, 2016, Vol. sept, p. 159-169, article id 579951Conference paper (Refereed)
    Abstract [en]

    Today’s automotive embedded systems comprise a multitude of functionalities, many with complex timing re- quirements. Besides task specific timing requirements, such ap- plications often have timing requirements for the propagation of data through a chain of tasks. An important metric for control applications is the data age, which is addressed in this work. The analysis of such systems is non-trivial because tasks involved in the data propagation may execute at different periods, which leads to over and undersampling within one chain. This work presents a novel method to compute worst- and best-case end-to-end latencies for such systems. A second contribution synthesizes job-level dependencies for such task sets in a way that data paths which exceed the age constraint are eliminated. An extensive evaluation is performed on synthetic task sets and the applicability to industrial applications is demonstrated in a case study.

  • 45.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Robert Bosch GmbH, Renningen, Germany.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Timing Analysis and Synthesis of Mixed Multi-Rate Effect Chains in MECHAniSer2016In: Open Demo Session of Real-Time Systems located at Real Time Systems Symposium (RTSS) RTSS@Work 2016, 2016Conference paper (Refereed)
    Abstract [en]

    The majority of embedded control systems are modeled with several chains of independently triggered tasks, also known as multi-rate effect chains. These chains have often stringent end-to-end timing requirements that should be satisfied before running the system. MECHAniSer is one of the tools that supports end-to-end timing analysis of such chains. In addition, the tool provides the possibility to synthesize job-level dependencies for these chains such that all end-to-end timing requirements are satisfied. In this paper we showcase an extension of MECHAniSer that supports the analysis of mixed chains that contain a mix of independent and dependent tasks.

  • 46.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Nelis, Vincent
    CISTER/INESC-TEC, ISEP, Portugal.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Pinho, Luis Miguel
    CISTER/INESC-TEC, ISEP, Portugal.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Investigation on AUTOSAR-Compliant Solutionsfor Many-Core Architectures2015In: Proceedings of the 18th Euromicro Conference on Digital System Design (DSD 2015), 2015Conference paper (Refereed)
    Abstract [en]

    As of today, AUTOSAR is the de facto standard inthe automotive industry, providing a common software architectureand development process for automotive applications. Whilethis standard is originally written for singlecore operated ElectronicControl Units (ECU), new guidelines and recommendationshave been added recently to provide support for multicore architectures.This update came as a response to the steady increase ofthe number and complexity of the software functions embedded inmodern vehicles, which call for the computing power of multicoreexecution environments. In this paper, we enumerate and analyzethe design options and the challenges of porting AUTOSAR-basedautomotive applications onto multicore platforms. In particular,we investigate those options when considering the emerging manycorearchitectures that provide a more scalable environment thanthe traditional multicore systems. Such platforms are suitableto enable massive parallel execution, and their design is moresuitable for partitioning and isolating the software components.

  • 47.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Nicolic, Borislav
    CISTER, INESC-TEC, ISEP, Portugal .
    Åkesson, Benny
    CISTER, INESC-TEC, ISEP, Portugal .
    Nélis, Vincent
    CISTER/INESC-TEC, ISEP, Portugal.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Contention-Free Execution of Automotive Applications on a Clustered Many-Core Platform2016In: 28th Euromicro Conference on Real-Time Systems ECRTS'16, Toulouse, France, 2016, p. 14-24Conference paper (Refereed)
    Abstract [en]

    Next generations of compute-intensive real-time applications in automotive systems will require more powerful computing platforms. One promising power-efficient solution for such applications is to use clustered many-core architectures. However, ensuring that real-time requirements are satisfied in the presence of contention in shared resources, such as memories, remains an open issue. This work presents a novel contention-free execution framework to execute automotive applications on such platforms. Privatization of memory banks together with defined access phases to shared memory resources is the backbone of the framework. An Integer Linear Programming (ILP) formulation is presented to find the optimal time-triggered schedule for the on-core execution as well as for the access to shared memory. Additionally a heuristic solution is presented that generates the schedule in a fraction of the time required by the ILP. Extensive evaluations show that the proposed heuristic performs only 0.5% away from the optimal solution while it outperforms a baseline heuristic by 67%. The applicability of the approach to industrially sized problems is demonstrated in a case study of a software for Engine Management Systems.

  • 48.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Nélis, Vincent
    CISTER/INESC-TEC, ISEP, Portugal.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Partitioning the Network-on-Chip to Enable Virtualization on Many-Core Processors2015In: The 6th International Real-Time Scheduling Open Problems Seminar RTSOPS'15, 2015Conference paper (Refereed)
    Abstract [en]

    Technological advances have increased the transistor density, thereby ushering in multi- and more recently many-core systems, distinguished by the presence of hundreds of cores on a single chip. For such a platform, the Network-on-Chip (NoC) has emerged as a scalable and efficient interconnect fabric to realize the communication across an ever increasing number of processor cores, memories, and specialized IP blocks both on- and off-chip. In this paper, we highlighted some key problems in NoC based architectures that must be addressed before the deployment of real-time applications onto these platforms becomes possible. A paradigm shift from function centric to data and communication centric approaches is required. Combining hardware and software based flow-regulation seems to be the only way to ensure that NoCs go beyond the best-effort service and address the requirements of diverse applications.

  • 49.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Khalilzad, Nima
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, Reinder J.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Technische Universiteit Eindhoven, Eindhoven, Netherlands.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Extended support for limited preemption fixed priority scheduling for OSEK/AUTOSAR-compliant operating systems2015In: 2015 10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015 - Proceedings, 2015, p. 207-217Conference paper (Refereed)
    Abstract [en]

    Fixed Priority Scheduling (FPS) is the de facto standard in industry and it is the scheduling algorithm used in OSEK/AUTOSAR. Applications in such systems are compositions of so called runnables, the functional entities of the system. Runnables are mapped to operating system tasks during system synthesis. In order to improve system performance it is proposed to execute runnables non-preemptively while varying the tasks threshold between runnables. This allows simpler resource access, can reduce the stack usage of the system, and improve the schedulability of the task sets. FPDS , as a special case of fixed-priority scheduling with deferred preemptions, executes subjobs non-preemptively and preemption points have preemption thresholds, providing exactly the proposed behavior. However OSEK/AUTOSAR-conform systems cannot execute such schedules. In this paper we present an approach allowing the execution of FPDS schedules. In our approach we exploit pseudo resources in order to implement FPDS . It is further shown that our optimal algorithm produces a minimum number of resource accesses. In addition, a simulation based evaluation is presented in which the number of resource accesses as well as the number of required pseudo-resources by the proposed algorithms are investigated. Finally, we report the overhead of resource access primitives using our measurements performed on an AUTOSARcompliant operating system.

  • 50.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Liu, Meng
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Adaptive Routing of Real-Time Traffic on a 2D-Mesh Based NoC2015In: The 21st IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, WiP RTCSA-wip'15, 2015Conference paper (Refereed)
1234567 1 - 50 of 337
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