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  • 1.
    Abbas, Muhammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. RISE Research Institutes of Sweden.
    Requirements-Level Reuse Recommendation and Prioritization of Product Line Assets2021Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Software systems often target a variety of different market segments. Targeting varying customer requirements requires a product-focused development process. Software Product Line (SPL) engineering is one possible approach based on reuse rationale to aid quick delivery of quality product variants at scale. SPLs reuse common features across derived products while still providing varying configuration options. The common features, in most cases, are realized by reusable assets. In practice, the assets are reused in a clone-and-own manner to reduce the upfront cost of systematic reuse. Besides, the assets are implemented in increments, and requirements prioritization also has to be done. In this context, the manual reuse analysis and prioritization process become impractical when the number of derived products grows. Besides, the manual reuse analysis process is time-consuming and heavily dependent on the experience of engineers.

    In this licentiate thesis, we study requirements-level reuse recommendation and prioritization for SPL assets in industrial settings. We first identify challenges and opportunities in SPLs where reuse is done in a clone-and-own manner.  We then focus on one of the identified challenges: requirements-based SPL assets reuse and provide automated support for identifying reuse opportunities for SPL assets based on requirements. Finally, we provide automated support for requirements prioritization in the presence of dependencies resulting from reuse.

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  • 2.
    Abbas, Muhammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. RISE Research Institutes of Sweden.
    Variability Aware Requirements Reuse Analysis2020In: roceedings - 2020 ACM/IEEE 42nd International Conference on Software Engineering: Companion, ICSE-Companion 2020, Seoul, South Korea: ACM , 2020, p. 190-193, article id 3381399Conference paper (Refereed)
    Abstract [en]

    Problem: The goal of a software product line is to aid quick and quality delivery of software products, sharing common features. Effectively achieving the above-mentioned goals requires reuse analysis of the product line features. Existing requirements reuse analysis approaches are not focused on recommending product line features, that can be reused to realize new customer requirements. Hypothesis: Given that the customer requirements are linked to product line features' description satisfying them: then the customer requirements can be clustered based on patterns and similarities, preserving the historic reuse information. New customer requirements can be evaluated against existing customer requirements and reuse of product line features can be recommended. Contributions: We treated the problem of feature reuse analysis as a text classification problem at the requirements-level. We use Natural Language Processing and clustering to recommend reuse of features based on similarities and historic reuse information. The recommendations can be used to realize new customer requirements.

  • 3.
    Abbas, Muhammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. RISE Research Institutes of Sweden.
    Ferrari, Alessio
    CNR-ISTI, Pisa, Italy.
    Shatnawi, Anas
    Berget-Levrault, Montpellier, France.
    Enoiu, Eduard Paul
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Saadatmand, Mehrdad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. RISE Research Institutes of Sweden.
    Is Requirements Similarity a Good Proxy for Software Similarity? An Empirical Investigation in Industry2021In: Requirements Engineering: Foundation for Software Quality / [ed] Dalpiaz, Fabiano and Spoletini, Paola (Eds.), Cham: Springer International Publishing , 2021, Vol. 12685, p. 3-18Conference paper (Refereed)
    Abstract [en]

    [Context and Motivation] Content-based recommender systems for requirements are typically built on the assumption that similar requirements can be used as proxies to retrieve similar software. When a new requirement is proposed by a stakeholder, natural language processing (NLP)-based similarity metrics can be exploited to retrieve existing requirements, and in turn, identify previously developed code. [Question/problem] Several NLP approaches for similarity computation are available, and there is little empirical evidence on the adoption of an effective technique in recommender systems specifically oriented to requirements-based code reuse. [Principal ideas/results] This study compares different state-of-the-art NLP approaches and correlates the similarity among requirements with the similarity of their source code. The evaluation is conducted on real-world requirements from two industrial projects in the railway domain. Results show that requirements similarity computed with the traditional tf-idf approach has the highest correlation with the actual software similarity in the considered context. Furthermore, results indicate a moderate positive correlation with Spearman's rank correlation coefficient of more than 0.5. [Contribution] Our work is among the first ones to explore the relationship between requirements similarity and software similarity. In addition, we also identify a suitable approach for computing requirements similarity that reflects software similarity well in an industrial context. This can be useful not only in recommender systems but also in other requirements engineering tasks in which similarity computation is relevant, such as tracing and categorization.

  • 4.
    Abbas, Muhammad
    et al.
    Research Institutes of Sweden Västerås, Sweden.
    Inayat, Irum
    National University of Computer & Emerging Sciences Islamabad, Pakistan.
    Jan, Naila
    National University of Computer & Emerging Sciences Islamabad, Pakistan.
    Saadatmand, Mehrdad
    Research Institutes of Sweden Västerås, Sweden.
    Enoiu, Eduard Paul
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    MBRP: Model-based Requirements Prioritization Using PageRank Algorithm2019In: Asia-Pacific Software Engineering Conference APSEC 2019, 2019, p. 31-38, article id 8945656Conference paper (Refereed)
    Abstract [en]

    Requirements prioritization plays an important role in driving project success during software development. Literature reveals that existing requirements prioritization approaches ignore vital factors such as interdependency between requirements. Existing requirements prioritization approaches are also generally time-consuming and involve substantial manual effort. Besides, these approaches show substantial limitations in terms of the number of requirements under consideration. There is some evidence suggesting that models could have a useful role in the analysis of requirements interdependency and their visualization, contributing towards the improvement of the overall requirements prioritization process. However, to date, just a handful of studies are focused on model-based strategies for requirements prioritization, considering only conflict-free functional requirements. This paper uses a meta-model-based approach to help the requirements analyst to model the requirements, stakeholders, and inter-dependencies between requirements. The model instance is then processed by our modified PageRank algorithm to prioritize the given requirements. An experiment was conducted, comparing our modified PageRank algorithm’s efficiency and accuracy with five existing requirements prioritization methods. Besides, we also compared our results with a baseline prioritized list of 104 requirements prepared by 28 graduate students. Our results show that our modified PageRank algorithm was able to prioritize the requirements more effectively and efficiently than the other prioritization methods.

  • 5.
    Abbas, Muhammad
    et al.
    RISE Research Institutes of Sweden, Västerås, Sweden.
    Jongeling, Robbert
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lindskog, Claes
    Bombardier Transportation AB, Sweden.
    Enoiu, Eduard Paul
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Saadatmand, Mehrdad
    RISE Research Institutes of Sweden, Västerås, Sweden.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Product Line Adoption in Industry: An Experience Report from the Railway Domain2020In: ACM International Conference Proceeding Series, 2020, Vol. F164267-A, p. 130-141Conference paper (Refereed)
    Abstract [en]

    The software system controlling a train is typically deployed on various hardware architectures and is required to process various signals across those deployments. Increases of such customization scenarios, as well as the needed adherence of the software to various safety standards in different application domains, has led to the adoption of product line engineering within the railway domain. This paper explores the current state-of-practice of software product line development within a team developing industrial embedded software for a train propulsion control system. Evidence is collected by means of a focus group session with several engineers and through inspection of archival data. We report several benefits and challenges experienced during product line adoption and deployment. Furthermore, we identify and discuss research opportunities, focusing in particular on the areas of product line evolution and test automation.

  • 6.
    Abbas, Muhammad
    et al.
    RISE Research Institutes of Sweden.
    Rauf, Abdul
    RISE Research Institute of Sweden.
    Saadatmand, Mehrdad
    RISE Research Institute of Sweden.
    Enoiu, Eduard Paul
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Keywords-based test categorization for Extra-Functional Properties2020In: IEEE 13th International Conference on Software Testing, Verification and Validation Workshops, ICSTW 2020, IEEE, 2020, p. 153-156, article id 9156019Conference paper (Refereed)
    Abstract [en]

    Categorizing existing test specifications can provide insights on coverage of the test suite to extra-functional properties. Manual approaches for test categorization can be time-consuming and prone to error. In this short paper, we propose a semi-automated approach for semantic keywords-based textual test categorization for extra-functional properties. The approach is the first step towards coverage-based test case selection based on extra-functional properties. We report a preliminary evaluation of industrial data for test categorization for safety aspects. Results show that keyword-based approaches can be used to categorize tests for extra-functional properties and can be improved by considering contextual information of keywords.

  • 7.
    Abbas, Muhammad
    et al.
    RISE, Sweden.
    Saadatmand, Mehrdad
    RISE, Sweden.
    Enoiu, Eduard Paul
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Requirements-Driven Reuse Recommendation2021In: Proceedings of the 25th ACM International Systems and Software Product Line Conference - Volume A, Association for Computing Machinery , 2021Conference paper (Refereed)
    Abstract [en]

    This tutorial explores requirements-based reuse recommendation for product line assets in the context of clone-and-own product lines.

  • 8.
    Abbas, Muhammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Saadatmand, Mehrdad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Enoiu, Eduard Paul
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lindskog, Claes
    Bombardier Transportation AB, Sweden.
    Automated Reuse Recommendation of Product Line Assets based on Natural Language Requirements2020In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2020, Vol. 12541, p. 173-189Conference paper (Refereed)
    Abstract [en]

    Software product lines (SPLs) are based on reuse rationale to aid quick and quality delivery of complex products at scale. Deriving a new product from a product line requires reuse analysis to avoid redundancy and support a high degree of assets reuse. In this paper, we propose and evaluate automated support for recommending SPL assets that can be reused to realize new customer requirements. Using the existing customer requirements as input, the approach applies natural language processing and clustering to generate reuse recommendations for unseen customer requirements in new projects. The approach is evaluated both quantitatively and qualitatively in the railway industry. Results show that our approach can recommend reuse with 74% accuracy and 57.4% exact match. The evaluation further indicates that the recommendations are relevant to engineers and can support the product derivation and feasibility analysis phase of the projects. The results encourage further study on automated reuse analysis on other levels of abstractions.

  • 9.
    Abbasi, S.
    et al.
    Islamic Azad University, Tehran, Iran.
    Rahmani, A. M.
    National Yunlin University of Science and Technology, Douliou, Yunlin, Taiwan.
    Balador, Ali
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. RISE Research Institute of Sweden, Västerås, Sweden.
    Sahafi, A.
    Islamic Azad University, Tehran, Iran.
    Internet of Vehicles: Architecture, services, and applications2021In: International Journal of Communication Systems, ISSN 1074-5351, E-ISSN 1099-1131, Vol. 34, no 10Article in journal (Refereed)
    Abstract [en]

    The connection between objects and information exchange has been possible in recent years, with the advent of the Internet of Things (IoT) in different industries. We can meet different requirements in each industry utilizing this feature. Intelligent transportation uses the Internet of Vehicles (IoV) as a solution for communication among vehicles. It improves traffic management applications and services to guarantee safety on roads. We categorize services, applications, and architectures and propose a taxonomy for IoV. Then, we study open issues and challenges for future works. We highlighted applications and services due to drivers' requirements and nonfunctional requirements, considering the qualitative characteristic. This paper summarizes the current state of the IoV in architectures, services, and applications. It can be a start view to provide the solutions for challenges in traffic management in cities. The present study is beneficial for smart city developments and management. According to this paper's result, the services and applications evaluate performance with 34% frequency, safety and data accuracy, and security with a 13% frequency in selected papers. These measurements are essential due to the IoV characteristics such as real-time operation, accident avoidance in applications, and complicated user data management. 

  • 10.
    Abbaspour Asadollah, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bugs and Debugging of Concurrent and Multicore Software2016Licentiate thesis, comprehensive summary (Other academic)
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  • 11.
    Abbaspour Asadollah, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Concurrency Bugs: Characterization, Debugging and Runtime Verification2018Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Concurrent software has been increasingly adopted in recent years, mainly due to the introduction of multicore platforms. However, concurrency bugs are still difficult to test and debug due to their complex interactions involving multiple threads (or tasks). Typically, real world concurrent software has huge state spaces. Thus, testing techniques and handling of concurrency bugs need to focus on exposing the bugs in this large space. However, existing solutions typically do not provide debugging information to developers (and testers) for understanding the bugs.

    Our work focuses on improving concurrent software reliability via three contributions: 1) An investigation of concurrent software challenges with the aim to help developers (and testers) to better understand concurrency bugs. We propose a classification of concurrency bugs and discuss observable properties of each type of bug. In addition, we identify a number of gaps in the body of knowledge on concurrent software bugs and their debugging. 2) Exploring concurrency related bugs in real-world software with respect to the reproducibility of bugs, severity of their consequence and effort required to fix them. Our findings here is that concurrency bugs are different from other bugs in terms of their fixing time and severity, while they are similar in terms of reproducibility. 3) A model for monitoring concurrency bugs and the implementation and evaluation of a related runtime verification tool to detect the bugs. In general, runtime verification techniques are used to (a) dynamically verify that the observed behaviour matches specified properties and (b) explicitly recognize understandable behaviors in the considered software. Our implemented tool is used to detect concurrency bugs in embedded software and is in its current form tailored for the FreeRTOS operating system. It helps developers and testers to automatically identify concurrency bugs and subsequently helps to reduce their finding and fixing time.

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  • 12.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Enoiu, Eduard Paul
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Causevic, Adnan
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Runtime Verification based Concurrency Bug Detector for FreeRTOS Embedded Software2018In: Proceedings - 17th International Symposium on Parallel and Distributed Computing, ISPDC 2018, 2018, p. 172-179, article id 8452035Conference paper (Refereed)
    Download full text (pdf)
    fulltext
  • 13.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Eldh, Sigrid
    Ericsson AB, Kista, Sweden.
    Towards Classification of Concurrency Bugs Based on Observable Properties2015In: Proceedings - 1st International Workshop on Complex Faults and Failures in Large Software Systems, COUFLESS 2015, 2015, p. 41-47Conference paper (Refereed)
    Abstract [en]

    In software engineering, classification is a way to find an organized structure of knowledge about objects. Classification serves to investigate the relationship between the items to be classified, and can be used to identify the current gaps in the field. In many cases users are able to order and relate objects by fitting them in a category. This paper presents initial work on a taxonomy for classification of errors (bugs) related to concurrent execution of application level software threads. By classifying concurrency bugs based on their corresponding observable properties, this research aims to examine and structure the state of the art in this field, as well as to provide practitioner support for testing and debugging of concurrent software. We also show how the proposed classification, and the different classes of bugs, relates to the state of the art in the field by providing a mapping of the classification to a number of recently published papers in the software engineering field.

  • 14.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Inam, Rafia
    Ericsson AB, Kista, Sweden.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Survey on Testing for Cyber Physical System2015In: Testing Software and Systems: 27th IFIP WG 6.1 International Conference, ICTSS 2015, Sharjah and Dubai, United Arab Emirates, November 23-25, 2015, Proceedings, 2015, p. 194-207Conference paper (Refereed)
    Abstract [en]

    Cyber Physical Systems (CPS) bridge the cyber-world of computing and communications with the physical world and require development of secure and reliable software. It asserts a big challenge not only on testing and verifying the correctness of all physical and cyber components of such big systems, but also on integration of these components. This paper develops a categorization of multiple levels of testing required to test CPS and makes a comparison of these levels with the levels of software testing based on the V-model. It presents a detailed state-of-the-art survey on the testing approaches performed on the CPS. Further, it provides challenges in CPS testing.

  • 15.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. RISE Acreo AB, Sweden.
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    GholamHosseini, Hamid
    Auckland University of Technology, Auckland, New Zealand.
    Naber, A.
    Chalmers University of Technology, Gothenburg, Sweden.
    Ortiz-Catalan, M.
    Chalmers University of Technology, Gothenburg, Sweden.
    Evaluation of surface EMG-based recognition algorithms for decoding hand movements2020In: Medical and Biological Engineering and Computing, ISSN 0140-0118, E-ISSN 1741-0444, Vol. 58, no 1, p. 83-100Article in journal (Refereed)
    Abstract [en]

    Myoelectric pattern recognition (MPR) to decode limb movements is an important advancement regarding the control of powered prostheses. However, this technology is not yet in wide clinical use. Improvements in MPR could potentially increase the functionality of powered prostheses. To this purpose, offline accuracy and processing time were measured over 44 features using six classifiers with the aim of determining new configurations of features and classifiers to improve the accuracy and response time of prosthetics control. An efficient feature set (FS: waveform length, correlation coefficient, Hjorth Parameters) was found to improve the motion recognition accuracy. Using the proposed FS significantly increased the performance of linear discriminant analysis, K-nearest neighbor, maximum likelihood estimation (MLE), and support vector machine by 5.5%, 5.7%, 6.3%, and 6.2%, respectively, when compared with the Hudgins’ set. Using the FS with MLE provided the largest improvement in offline accuracy over the Hudgins feature set, with minimal effect on the processing time. Among the 44 features tested, logarithmic root mean square and normalized logarithmic energy yielded the highest recognition rates (above 95%). We anticipate that this work will contribute to the development of more accurate surface EMG-based motor decoding systems for the control prosthetic hands.

  • 16.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Saadatmand, Mehrdad
    SICS Swedish ICT, Västerås, Sweden.
    Eldh, Sigrid
    Ericsson AB, Kista, Sweden.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Model for Systematic Monitoring and Debugging of Starvation Bugs in Multicore Software2016In: 2016 ASE Workshop on Specification, Comprehension, Testing and Debugging of Concurrent Programs SCTDCP2016, 2016Conference paper (Refereed)
    Abstract [en]

    With the development of multicore hardware, concurrent, parallel and multicore software are becoming increasingly popular. Software companies are spending a huge amount of time and resources to nd and debug the bugs. Among all types of software bugs, concurrency bugs are also important and troublesome. This type of bugs is increasingly becoming an issue particularly due to the growing prevalence of multicore hardware. In this position paper, we propose a model for monitoring and debugging Starvation bugs as a type of concurrency bugs in multicore software. The model is composed into three phases: monitoring, detecting and debugging. The monitoring phase can support detecting phase by storing collected data from the system execution. The detecting phase can support debugging phase by comparing the stored data with starvation bug's properties, and the debugging phase can help in reproducing and removing the Starvation bug from multicore software. Our intention is that our model is the basis for developing tool(s) to enable solving Starvation bugs in software for multicore platforms.

  • 17.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Eldh, S.
    Ericsson AB, Kista, Sweden.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Runtime Verification Tool for Detecting Concurrency Bugs in FreeRTOS Embedded Software2018In: Proceedings - 17th International Symposium on Parallel and Distributed Computing, ISPDC 2018, Institute of Electrical and Electronics Engineers Inc. , 2018, p. 172-179, article id 8452035Conference paper (Refereed)
    Abstract [en]

    This article presents a runtime verification tool for embedded software executing under the open source real-time operating system FreeRTOS. The tool detects and diagnoses concurrency bugs such as deadlock, starvation, and suspension based-locking. The tool finds concurrency bugs at runtime without debugging and tracing the source code. The tool uses the Tracealyzer tool for logging relevant events. Analysing the logs, our tool can detect the concurrency bugs by applying algorithms for diagnosing each concurrency bug type individually. In this paper, we present the implementation of the tool, as well as its functional architecture, together with illustration of its use. The tool can be used during program testing to gain interesting information about embedded software executions. We present initial results of running the tool on some classical bug examples running on an AVR 32-bit board SAM4S. 

  • 18.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Eldh, S.
    Ericsson AB, Stockholm, Sweden.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Concurrency bugs in open source software: a case study2017In: Journal of Internet Services and Applications, ISSN 1867-4828, E-ISSN 1869-0238, Vol. 8, no 1, article id 4Article in journal (Refereed)
    Abstract [en]

    Concurrent programming puts demands on software debugging and testing, as concurrent software may exhibit problems not present in sequential software, e.g., deadlocks and race conditions. In aiming to increase efficiency and effectiveness of debugging and bug-fixing for concurrent software, a deep understanding of concurrency bugs, their frequency and fixing-times would be helpful. Similarly, to design effective tools and techniques for testing and debugging concurrent software, understanding the differences between non-concurrency and concurrency bugs in real-word software would be useful. This paper presents an empirical study focusing on understanding the differences and similarities between concurrency bugs and other bugs, as well as the differences among various concurrency bug types in terms of their severity and their fixing time, and reproducibility. Our basis is a comprehensive analysis of bug reports covering several generations of five open source software projects. The analysis involves a total of 11860 bug reports from the last decade, including 351 reports related to concurrency bugs. We found that concurrency bugs are different from other bugs in terms of their fixing time and severity while they are similar in terms of reproducibility. Our findings shed light on concurrency bugs and could thereby influence future design and development of concurrent software, their debugging and testing, as well as related tools.

  • 19.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Eldh, Sigrid
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Ericsson AB, Kista, Sweden .
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Afza, Wasif
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    10 Years of research on debugging concurrent and multicore software: a systematic mapping study2017In: Software quality journal, ISSN 0963-9314, E-ISSN 1573-1367, Vol. 25, no 1, p. 49-82Article in journal (Refereed)
    Abstract [en]

    Debugging – the process of identifying, localizing and fixing bugs – is a key activity in software development. Due to issues such as non-determinism and difficulties of reproducing failures, debugging concurrent software is significantly more challenging than debugging sequential software. A number of methods, models and tools for debugging concurrent and multicore software have been proposed, but the body of work partially lacks a common terminology and a more recent view of the problems to solve. This suggests the need for a classification, and an up-to-date comprehensive overview of the area. 

    This paper presents the results of a systematic mapping study in the field of debugging of concurrent and multicore software in the last decade (2005– 2014). The study is guided by two objectives: (1) to summarize the recent publication trends and (2) to clarify current research gaps in the field.

    Through a multi-stage selection process, we identified 145 relevant papers. Based on these, we summarize the publication trend in the field by showing distribution of publications with respect to year , publication venues , representation of academia and industry , and active research institutes . We also identify research gaps in the field based on attributes such as types of concurrency bugs, types of debugging processes , types of research  and research contributions.

    The main observations from the study are that during the years 2005–2014: (1) there is no focal conference or venue to publish papers in this area, hence a large variety of conferences and journal venues (90) are used to publish relevant papers in this area; (2) in terms of publication contribution, academia was more active in this area than industry; (3) most publications in the field address the data race bug; (4) bug identification is the most common stage of debugging addressed by articles in the period; (5) there are six types of research approaches found, with solution proposals being the most common one; and (6) the published papers essentially focus on four different types of contributions, with ”methods” being the type most common one.

    We can further conclude that there is still quite a number of aspects that are not sufficiently covered in the field, most notably including (1) exploring correction  and fixing bugs  in terms of debugging process; (2) order violation, suspension  and starvation  in terms of concurrency bugs; (3) validation and evaluation research  in the matter of research type; (4) metric  in terms of research contribution. It is clear that the concurrent, parallel and multicore software community needs broader studies in debugging.This systematic mapping study can help direct such efforts.

  • 20.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Eldh, Sigrid
    Ericsson AB, Kista, Sweden.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Paul Enoiu, Eduard
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Study on Concurrency Bugs in an Open Source Software2016In: IFIP Advances in Information and Communication Technology, vol. 472, 2016, Vol. 472, p. 16-31Conference paper (Refereed)
    Abstract [en]

    Concurrent programming puts demands on software debugging and testing, as concurrent software may exhibit problems not present in sequential software, e.g., deadlocks and race conditions. In aiming to increase efficiency and effectiveness of debugging and bug-fixing for concurrent software, a deep understanding of concurrency bugs, their frequency and fixingtimes would be helpful. Similarly, to design effective tools and techniques for testing and debugging concurrent software understanding the differences between non-concurrency and concurrency bugs in real-word software would be useful.

  • 21.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Runtime Verification for Detecting Suspension Bugs in Multicore and Parallel Software2017In: Proceedings - 10th IEEE International Conference on Software Testing, Verification and Validation Workshops, ICSTW 2017, 2017, p. 77-80Conference paper (Refereed)
    Abstract [en]

    Multicore hardware development increases the popularity of parallel and multicore software, while testing and debugging the software become more difficult, frustrating and costly. Among all types of software bugs, concurrency bugs are both important and troublesome. This type of bugs is increasingly becoming an issue, particularly due to the growing prevalence of multicore hardware. Suspension-based-locking bug is one type of concurrency bugs. This position paper proposes a model based on runtime verification and reflection technique in the context of multicore and parallel software to monitor and detect suspension-based-locking bugs. The model is not only able to detect faults, but also diagnose and even repair them. The model is composed of four layers: Logging, Monitoring, Suspension Bug Diagnosis and Mitigation. The logging layer will observe the events and save them into a file system. The monitoring layer will detect the presents of bugs in the software. The suspension bug diagnosis will identify Suspension bugs by comparing the captured data with the suspension bug properties. Finally, the mitigation layer will reconfigure the software to mitigate the suspension bugs. A functional architecture of a runtime verification tool is also proposed in this paper. This architecture is based on the proposed model and is comprised of different modules. 

  • 22.
    Abbaspour Gildeh, Saedeh
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Fotouhi, Faranak
    Fotouhi, Hossein
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Vahabi, Maryam
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Deep learning-based motion activity recognition using smartphone sensors2020In: 12th International Conference on e-Health e-Health'20, 2020Conference paper (Refereed)
  • 23.
    Abbaspour, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Electromyogram Signal Enhancement and Upper-Limb Myoelectric Pattern Recognition2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Losing a limb causes difficulties in our daily life. To regain the ability to live an independent life, artificial limbs have been developed. Hand prostheses belong to a group of artificial limbs that can be controlled by the user through the activity of the remnant muscles above the amputation. Electromyogram (EMG) is one of the sources that can be used for control methods for hand prostheses. Surface EMGs are powerful, non-invasive tools that provide information about neuromuscular activity of the subjected muscle, which has been essential to its use as a source of control for prosthetic limbs. However, the complexity of this signal introduces a big challenge to its applications. EMG pattern recognition to decode different limb movements is an important advancement regarding the control of powered prostheses. It has the potential to enable the control of powered prostheses using the generated EMG by muscular contractions as an input. However, its use has yet to be transitioned into wide clinical use. Different algorithms have been developed in state of the art to decode different movements; however, the challenge still lies in different stages of a successful hand gesture recognition and improvements in these areas could potentially increase the functionality of powered prostheses. This thesis firstly focuses on improving the EMG signal’s quality by proposing novel and advanced filtering techniques. Four efficient approaches (adaptive neuro-fuzzy inference system-wavelet, artificial neural network-wavelet, adaptive subtraction and automated independent component analysis-wavelet) are proposed to improve the filtering process of surface EMG signals and effectively eliminate ECG interferences. Then, the offline performance of different EMG-based recognition algorithms for classifying different hand movements are evaluated with the aim of obtaining new myoelectric control configurations that improves the recognition stage. Afterwards, to gain proper insight on the implementation of myoelectric pattern recognition, a wide range of myoelectric pattern recognition algorithms are investigated in real time. The experimental result on 15 healthy volunteers suggests that linear discriminant analysis (LDA) and maximum likelihood estimation (MLE) outperform other classifiers. The real-time investigation illustrates that in addition to the LDA and MLE, multilayer perceptron also outperforms the other algorithms when compared using classification accuracy and completion rate.

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  • 24.
    Abbaspour, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Evaluation of surface EMG-based recognition algorithms for decoding hand movementsManuscript (preprint) (Other academic)
  • 25.
    Abbaspour, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Proposing Combined Approaches to Remove ECG Artifacts from Surface EMG Signals2015Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Electromyography (EMG) is a tool routinely used for a variety of applications in a very large breadth of disciplines. However, this signal is inevitably contaminated by various artifacts originated from different sources. Electrical activity of heart muscles, electrocardiogram (ECG), is one of sources which affects the EMG signals due to the proximity of the collection sites to the heart and makes its analysis non-reliable. Different methods have been proposed to remove ECG artifacts from surface EMG signals; however, in spite of numerous attempts to eliminate or reduce this artifact, the problem of accurate and effective de-noising of EMG still remains a challenge. In this study common methods such as high pass filter (HPF), gating method, spike clipping, hybrid technique, template subtraction, independent component analysis (ICA), wavelet transform, wavelet-ICA, artificial neural network (ANN), and adaptive noise canceller (ANC) and adaptive neuro-fuzzy inference system (ANFIS) are used to remove ECG artifacts from surface EMG signals and their accuracy and effectiveness is investigated. HPF, gating method and spike clipping are fast; however they remove useful information from EMG signals. Hybrid technique and ANC are time consuming. Template subtraction requires predetermined QRS pattern. Using wavelet transform some artifacts remain in the original signal and part of the desired signal is removed. ICA requires multi-channel signals. Wavelet-ICA approach does not require multi-channel signals; however, it is user-dependent. ANN and ANFIS have good performance, but it is possible to improve their results by combining them with other techniques. For some applications of EMG signals such as rehabilitation, motion control and motion prediction, the quality of EMG signals is very important. Furthermore, the artifact removal methods need to be online and automatic. Hence, efficient methods such as ANN-wavelet, adaptive subtraction and automated wavelet-ICA are proposed to effectively eliminate ECG artifacts from surface EMG signals. To compare the results of the investigated methods and the proposed methods in this study, clean EMG signals from biceps and deltoid muscles and ECG artifacts from pectoralis major muscle are recorded from five healthy subjects to create 10 channels of contaminated EMG signals by adding the recorded ECG artifacts to the clean EMG signals. The artifact removal methods are also applied to the 10 channels of real contaminated EMG signals from pectoralis major muscle of the left side. Evaluation criteria such as signal to noise ratio, relative error, correlation coefficient, elapsed time and power spectrum density are used to evaluate the performance of the proposed methods. It is found that the performance of the proposed ANN-wavelet method is superior to the other methods with a signal to noise ratio, relative error and correlation coefficient of 15.53, 0.01 and 0.98 respectively.

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  • 26.
    Abbaspour, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Surface EMG signal processing: Removing ECG interferences and classifying hand movements2017In: Medicinteknikdagarna 2017 MTD 2017, Västerås, Sweden, 2017Conference paper (Refereed)
  • 27.
    Abbaspour, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Fallah, Ali
    Amirkabir University of Technology, Tehran, Iran.
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    GholamHosseini, Hamid
    Auckland University of Technology, Auckland, New Zealand.
    A Novel Approach for Removing ECG Interferences from Surface EMG signals Using a Combined ANFIS and Wavelet2016In: Journal of Electromyography & Kinesiology, ISSN 1050-6411, E-ISSN 1873-5711, Vol. 26, p. 52-59Article in journal (Refereed)
    Abstract [en]

    In recent years, the removal of electrocardiogram (ECG) interferences from electromyogram (EMG) signals has been given large consideration. Where the quality of EMG signal is of interest, it is important to remove ECG interferences from EMG signals. In this paper, an efficient method based on a combination of adaptive neuro-fuzzy inference system (ANFIS) and wavelet transform is proposed to effectively eliminate ECG interferences from surface EMG signals. The proposed approach is compared with other common methods such as high-pass filter, artificial neural network, adaptive noise canceller, wavelet transform, subtraction method and ANFIS. It is found that the performance of the proposed ANFIS-wavelet method is superior to the other methods with the signal to noise ratio and relative error of 14.97 dB and 0.02 respectively and a significantly higher correlation coefficient (p < 0.05).

  • 28.
    Abbaspour, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Engineering Department, University of Qom, Iran.
    Fotouhi, F.
    Engineering Department, University of Qom, Iran.
    Sedaghatbaf, A.
    RISE Research Institutes of Sweden, Sweden.
    Fotouhi, Hossein
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Vahabi, Maryam
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. ABB Corporate Research, Sweden.
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A comparative analysis of hybrid deep learning models for human activity recognition2020In: Sensors, E-ISSN 1424-8220, Vol. 20, no 19, p. 1-14, article id 5707Article in journal (Refereed)
    Abstract [en]

    Recent advances in artificial intelligence and machine learning (ML) led to effective methods and tools for analyzing the human behavior. Human Activity Recognition (HAR) is one of the fields that has seen an explosive research interest among the ML community due to its wide range of applications. HAR is one of the most helpful technology tools to support the elderly’s daily life and to help people suffering from cognitive disorders, Parkinson’s disease, dementia, etc. It is also very useful in areas such as transportation, robotics and sports. Deep learning (DL) is a branch of ML based on complex Artificial Neural Networks (ANNs) that has demonstrated a high level of accuracy and performance in HAR. Convolutional Neural Networks (CNNs) and Recurrent Neural Networks (RNNs) are two types of DL models widely used in the recent years to address the HAR problem. The purpose of this paper is to investigate the effectiveness of their integration in recognizing daily activities, e.g., walking. We analyze four hybrid models that integrate CNNs with four powerful RNNs, i.e., LSTMs, BiLSTMs, GRUs and BiGRUs. The outcomes of our experiments on the PAMAP2 dataset indicate that our proposed hybrid models achieve an outstanding level of performance with respect to several indicative measures, e.g., F-score, accuracy, sensitivity, and specificity. © 2020 by the authors. Licensee MDPI, Basel, Switzerland.

  • 29.
    Abbaspour, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    GholamHosseini, Hamid
    Mälardalen University, School of Innovation, Design and Engineering. School of Engineering, Auckland University of TechnologyAuckland, New Zealand .
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Evaluation of wavelet based methods in removing motion artifact from ECG signal2015In: IFMBE Proceedings, 2015, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Accurate recording and precise analysis of the electrocardiogram (ECG) signals are crucial in the pathophysiological study and clinical treatment. These recordings are often corrupted by different artifacts. The aim of this study is to propose two different methods, wavelet transform based on nonlinear thresholding and a combination method using wavelet and independent component analysis (ICA), to remove motion artifact from ECG signals. To evaluate the performance of the proposed methods, the developed techniques are applied to the real and simulated ECG data. The results of this evaluation are presented using quantitative and qualitative criteria. The results show that the proposed methods are able to reduce motion artifacts in ECG signals. Signal to noise ratio (SNR) of the wavelet technique is equal to 13.85. The wavelet-ICA method performed better with SNR of 14.23.

  • 30.
    Abbaspour, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Electromyography signal analysis: Electrocardiogram artifact removal and classifying hand movements2018In: World Congress on Medical Physics and Biomedical Engineering IUPESM, 2018Conference paper (Refereed)
  • 31.
    Abbaspour, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    GholamHosseini, Hamid
    Auckland University of Technology, New Zealand.
    ECG Artifact Removal from Surface EMG Signal Using an Automated Method Based on Wavelet-ICA2015In: Studies in Health Technology and Informatics, Volume 211, 2015, p. 91-97Conference paper (Refereed)
    Abstract [en]

    This study aims at proposing an efficient method for automated electrocardiography (ECG) artifact removal from surface electromyography (EMG) signals recorded from upper trunk muscles. Wavelet transform is applied to the simulated data set of corrupted surface EMG signals to create multidimensional signal. Afterward, independent component analysis (ICA) is used to separate ECG artifact components from the original EMG signal. Components that correspond to the ECG artifact are then identified by an automated detection algorithm and are subsequently removed using a conventional high pass filter. Finally, the results of the proposed method are compared with wavelet transform, ICA, adaptive filter and empirical mode decomposition-ICA methods. The automated artifact removal method proposed in this study successfully removes the ECG artifacts from EMG signals with a signal to noise ratio value of 9.38 while keeping the distortion of original EMG to a minimum.

  • 32.
    Abbaspour, Sara
    et al.
    Massachusetts Gen Hosp, Dept Neurol, Boston, MA 02114 USA.;Harvard Med Sch, Div Sleep Med, Boston, MA 02114 USA..
    Naber, Autumn
    Ctr Bion & Pain Res, S-43180 Molndal, Sweden.;Chalmers Univ Technol, Dept Elect Engn, S-41296 Gothenburg, Sweden..
    Ortiz-Catalan, Max
    Ctr Bion & Pain Res, S-43180 Molndal, Sweden.;Chalmers Univ Technol, Dept Elect Engn, S-41296 Gothenburg, Sweden.;Sahlgrens Univ Hosp, Operat Area 3, S-43180 Molndal, Sweden.;Univ Gothenburg, Sahlgrenska Acad, Inst Clin Sci, Dept Orthopaed, S-43180 Molndal, Sweden..
    GholamHosseini, Hamid
    Auckland Univ Technol, Dept Elect & Elect Engn, Auckland 1010, New Zealand..
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Real-Time and Offline Evaluation of Myoelectric Pattern Recognition for the Decoding of Hand Movements2021In: Sensors, E-ISSN 1424-8220, Vol. 21, no 16, article id 5677Article in journal (Refereed)
    Abstract [en]

    Pattern recognition algorithms have been widely used to map surface electromyographic signals to target movements as a source for prosthetic control. However, most investigations have been conducted offline by performing the analysis on pre-recorded datasets. While real-time data analysis (i.e., classification when new data becomes available, with limits on latency under 200-300 milliseconds) plays an important role in the control of prosthetics, less knowledge has been gained with respect to real-time performance. Recent literature has underscored the differences between offline classification accuracy, the most common performance metric, and the usability of upper limb prostheses. Therefore, a comparative offline and real-time performance analysis between common algorithms had yet to be performed. In this study, we investigated the offline and real-time performance of nine different classification algorithms, decoding ten individual hand and wrist movements. Surface myoelectric signals were recorded from fifteen able-bodied subjects while performing the ten movements. The offline decoding demonstrated that linear discriminant analysis (LDA) and maximum likelihood estimation (MLE) significantly (p < 0.05) outperformed other classifiers, with an average classification accuracy of above 97%. On the other hand, the real-time investigation revealed that, in addition to the LDA and MLE, multilayer perceptron also outperformed the other algorithms and achieved a classification accuracy and completion rate of above 68% and 69%, respectively.

  • 33.
    Abdullah, Syed Md Jakaria
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Moghaddami Khalilzad, Nima
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Towards Implementation of Virtual-Clustered Multiprocessor Scheduling in Linux2013In: Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, SIES 2013, 2013, p. 97-100Conference paper (Refereed)
    Abstract [en]

    Cluster based multiprocessor scheduling can be seen as a hybrid approach combining benefits of both partitioned and global scheduling. Virtual clustering further enhances it by providing dynamic cluster resource allocation and applying hierarchical scheduling techniques. Over the years, the study of virtual cluster scheduling has been limited to theoretical analysis. In this paper, we present our initial ideas about implementing virtual cluster scheduling in Linux. The purpose of this implementation is twofold: (i) we would like to demonstrate the feasibility of its implementation in an operating system, without modifying the kernel source code, (ii) we present practical insights on the overhead of implementing this framework.

  • 34.
    Abrahamsson, H.
    et al.
    RISE, SICS, Germany.
    Abdesslem, F. B.
    RISE, SICS, Germany.
    Ahlgren, B.
    RISE, SICS, Germany.
    Brunstrom, A.
    Karlstad University, Sweden.
    Marsh, I.
    RISE, SICS, Germany.
    Björkman, Mats
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Connected Vehicles in Cellular Networks: Multi-Access Versus Single-Access Performance2018In: TMA 2018 - Proceedings of the 2nd Network Traffic Measurement and Analysis Conference, Institute of Electrical and Electronics Engineers Inc. , 2018Conference paper (Refereed)
    Abstract [en]

    Connected vehicles can make roads traffic safer and more efficient, but require the mobile networks to handle time-critical applications. Using the MONROE mobile broadband measurement testbed we conduct a multi-access measurement study on buses. The objective is to understand what network performance connected vehicles can expect in today's mobile networks, in terms of transaction times and availability. The goal is also to understand to what extent access to several operators in parallel can improve communication performance. In our measurement experiments we repeatedly transfer warning messages from moving buses to a stationary server. We triplicate the messages and always perform three transactions in parallel over three different cellular operators. This creates a dataset with which we can compare the operators in an objective way and with which we can study the potential for multi-access. In this paper we use the triple-access dataset to evaluate single-access selection strategies, where one operator is chosen for each transaction. We show that if we have access to three operators and for each transaction choose the operator with best access technology and best signal quality then we can significantly improve availability and transaction times compared to the individual operators. The median transaction time improves with 6% compared to the best single operator and with 61% compared to the worst single operator. The 90-percentile transaction time improves with 23% compared to the best single operator and with 65% compared to the worst single operator.

  • 35.
    Achuthan, K.
    et al.
    Amrita Center for Cybersecurity Systems and Networks, Kerala, India.
    Ramesh, M. V.
    Amrita Center for International Programs, Kerala, India.
    Punnekkat, Sasikumar
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Raman, R.
    Center for Research in Advanced Technologies for Education, Kerala, India.
    Internationalizing engineering education with phased study programs: India-European experience2015In: Proceedings - Frontiers in Education Conference, FIE, 2015, no FebruaryConference paper (Refereed)
    Abstract [en]

    Most of the critical challenges seen in the past decades have impacted citizens in a global way. Given shrinking resources, educationists find preparing students for the global market place a formidable challenge. Hence exposing students to multi-lateral educational initiatives are critical to their growth, understanding and future contributions. This paper focuses on European Union's Erasmus Mundus programs, involving academic cooperation amongst international universities in engineering programs. A phased undergraduate engineering program with multiple specializations is analyzed within this context. Based on their performance at the end of first phase, selected students were provided opportunities using scholarship to pursue completion of their degree requirements at various European universities. This paper will elaborate the impact of differing pedagogical interventions, language and cultural differences amongst these countries on students in diverse engineering disciplines. The data presented is based on on the feedback analysis from Eramus Mundus students (N=121) that underwent the mobility programs. The findings have given important insights into the structure of the initiative and implications for academia and education policy makers for internationalizing engineering education. These included considering digital interventions such as MOOCs (Massive Open Online Courses) and Virtual Laboratory (VL) initiatives for systemic reorganization of engineering education.

  • 36.
    Achuthan, Krishnashree
    et al.
    Amrita Vishwa Vidyapeetham, Amrita Ctr Cybersecur Syst & Networks, Kollam, Kerala, India..
    Ramesh, Maneesha V.
    Amrita Vishwa Vidyapeetham, Amrita Ctr Int Programs, Kollam, Kerala, India..
    Punnekkat, Sasikumar
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Raman, Raghu
    Amrita Vishwa Vidyapeetham, Ctr Res Adv Technol Educ, Kollam, Kerala, India..
    Internationalizing Engineering Education With Phased Study Programs: India-European Experience2014In: 2014 IEEE FRONTIERS IN EDUCATION CONFERENCE (FIE), IEEE , 2014, p. 295-301Conference paper (Refereed)
    Abstract [en]

    Most of the critical challenges seen in the past decades have impacted citizens in a global way. Given shrinking resources, educationists find preparing students for the global market place a formidable challenge. Hence exposing students to multi-lateral educational initiatives are critical to their growth, understanding and future contributions. This paper focuses on European Union's Erasmus Mundus programs, involving academic cooperation amongst international universities in engineering programs. A phased undergraduate engineering program with multiple specializations is analyzed within this context. Based on their performance at the end of first phase, selected students were provided opportunities using scholarship to pursue completion of their degree requirements at various European universities. This paper will elaborate the impact of differing pedagogical interventions, language and cultural differences amongst these countries on students in diverse engineering disciplines. The data presented is based on on the feedback analysis from Eramus Mundus students (N = 121) that underwent the mobility programs. The findings have given important insights into the structure of the initiative and implications for academia and education policy makers for internationalizing engineering education. These included considering digital interventions such as MOOCs (Massive Open Online Courses) and Virtual Laboratory (VL) initiatives for systemic reorganization of engineering education.

  • 37.
    Addazi, Lorenzo
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Cicchetti, Antonio
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Systematic Evaluation of Model Comparison Algorithms using Model Generation2020In: Journal of Object Technology, E-ISSN 1660-1769, Vol. 19, no 2Article in journal (Refereed)
    Abstract [en]

    Model-Driven Engineering promotes the migration from code-centric to model-based software development. Systems consist of model collections integrating different concerns and perspectives, while semi-automated model transformations analyse quality attributes and generate executable code combining the information from these. Raising the abstraction level to models requires appropriate management technologies supporting the various software development activities. Among these, model comparison represents one of the most challenging tasks and plays an essential role in various modelling activities. Its hardness led researchers to propose a multitude of approaches adopting different approximation strategies and exploiting specific knowledge of the involved models. In this respect, almost no support is provided for the systematic evaluation of comparison approaches against specific scenarios and modelling practices, namely benchmarks. In this article we propose Benji, a framework for the automated generation of model comparison benchmarks. In particular, by giving a set of difference patterns and an initial model, users can generate model manipulation scenarios resulting from the application of the patterns on the model. The generation support provided by the framework obeys specific design principles that are considered as essential properties for the systematic evaluation of model comparison solutions, and are inherited from the general principles coming from evidence-based software engineering. The framework is validated through representative scenarios of model comparison benchmark generations.

  • 38.
    Addazi, Lorenzo
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Cicchetti, Antonio
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Using Benji to systematically evaluate model comparison algorithms2020In: Proceedings - 23rd ACM/IEEE International Conference on Model Driven Engineering Languages and Systems, MODELS-C 2020 - Companion Proceedings, Association for Computing Machinery, Inc , 2020, p. 56-60Conference paper (Refereed)
    Abstract [en]

    Model comparison is a critical task in model-driven engineering. Its correctness enables an effective management of model evolution, synchronisation, and even other tasks, such as model transformation testing. The literature is rich as concerns comparison algorithms approaches, however the same cannot be said for their systematic evaluation. In this paper we present Benji, a tool for the generation of model comparison benchmarks. In particular, Benji provides domain-specific languages to design experiments in terms of input models and possible manipulations, and based on those generates corresponding benchmark cases. In this way, the experiment specification can be exploited as a systematic way to evaluate available comparison algorithms against the problem under study.

  • 39.
    Addazi, Lorenzo
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Cicchetti, Antonio
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. IS (Embedded Systems).
    Di Rocco, Juri
    University of L’Aquila, Italy.
    Di Ruscio, Davide
    University of L’Aquila, Italy.
    Iovino, Ludovico
    University of L’Aquila, Italy.
    Pierantonio, Alfonso
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. University of L’Aquila, Italy.
    Semantic-based Model Matching with EMFCompare2016In: CEUR Workshop Proceedings (CEUR-WS.org), Saint Malo, France: CEUR-WS , 2016, Vol. 1706, p. 40-49Conference paper (Refereed)
  • 40.
    Addazi, Lorenzo
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ciccozzi, Federico
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Blended graphical and textual modelling for UML profiles: A proof-of-concept implementation and experiment2021In: Journal of Systems and Software, ISSN 0164-1212, E-ISSN 1873-1228, Vol. 175, article id 110912Article in journal (Refereed)
    Abstract [en]

    Domain-specific modelling languages defined by extending or constraining the Unified Modelling Language (UML) through the profiling mechanism have historically relied on graphical notations to maximise human understanding and facilitate communication among stakeholders. Other notations, such as text-, form-, or table-based are, however, often preferred for specific modelling purposes, due to the nature of a specific domain or the available tooling, or for personal preference. Currently, the state of the art support for UML-based languages provides an almost completely detached, or even entirely mutually exclusive, use of graphical and textual modelling. This becomes inadequate when dealing with the development of modern systems carried out by heterogeneous stakeholders. Our intuition is that a modelling framework based on seamless blended multi-notations can disclose several benefits, among which: flexible separation of concerns, multi-view modelling based on multiple notations, convenient text-based editing operations (inside and outside the modelling environment), and eventually faster modelling activities. In this paper we report on: (i) a proof-of-concept implementation of a framework for UML and profiles modelling using blended textual and graphical notations, and (ii) an experiment on the framework, which eventually shows that blended multi-notation modelling performs better than standard single-notation modelling.

  • 41.
    Addazi, Lorenzo
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ciccozzi, Federico
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Langer, Philip
    EclipsSource, Austria.
    Posse, Ernesto
    Zeligsoft, Canada.
    Towards Seamless Hybrid Graphical-Textual Modelling for UML and Profiles2017In: Lecture Notes in Computer Science, vol. 10376, Springer, 2017, p. 20-33Chapter in book (Refereed)
    Abstract [en]

    Domain-specific modelling languages, in particular those described in terms of UML profiles, use graphical notations to maximise human understanding and facilitate communication among stakeholders. Nevertheless, textual notations are preferred for specific purposes, due to the nature of a specific domain, or for personal preference. The mutually exclusive use of graphical or textual modelling is not sufficient for the development of complex systems developed by large heterogeneous teams. We envision a modern modelling framework supporting seamless hybrid graphical and textual modelling. Such a framework would provide several benefits, among which: flexible separation of concerns, multi-view modelling based on multiple notations, convenient text-based editing operations, and text-based model editing outside the modelling environment, and faster modelling activities. In this paper we describe our work towards such a framework for UML and profiles. The uniqueness is that both graphical and textual modelling are done on a common persistent model resource, thus dramatically reducing the need for synchronisation among the two notations.

  • 42.
    Addazi, Lorenzo
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ciccozzi, Federico
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lisper, Björn
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Executable modelling for highly parallel accelerators2019In: Proceedings - 2019 ACM/IEEE 22nd International Conference on Model Driven Engineering Languages and Systems Companion, MODELS-C 2019, Institute of Electrical and Electronics Engineers Inc. , 2019, p. 318-321, article id 8904827Conference paper (Refereed)
    Abstract [en]

    High-performance embedded computing is developing rapidly since applications in most domains require a large and increasing amount of computing power. On the hardware side, this requirement is met by the introduction of heterogeneous systems, with highly parallel accelerators that are designed to take care of the computation-heavy parts of an application. There is today a plethora of accelerator architectures, including GPUs, many-cores, FPGAs, and domain-specific architectures such as AI accelerators. They all have their own programming models, which are typically complex, low-level, and involve explicit parallelism. This yields error-prone software that puts the functional safety at risk, unacceptable for safety-critical embedded applications. In this position paper we argue that high-level executable modelling languages tailored for parallel computing can help in the software design for high performance embedded applications. In particular, we consider the data-parallel model to be a suitable candidate, since it allows very abstract parallel algorithm specifications free from race conditions. Moreover, we promote the Action Language for fUML (and thereby fUML) as suitable host language.

  • 43.
    Afifi, S.
    et al.
    Auckland University of Technology, Auckland, New Zealand.
    GholamHosseini, Hamid
    Auckland University of Technology, Auckland, New Zealand.
    Sinha, R.
    Auckland University of Technology, Auckland, New Zealand.
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Novel Medical Device for Early Detection of Melanoma2019In: Studies in Health Technology and Informatics, ISSN 0926-9630, E-ISSN 1879-8365, Vol. 261, p. 122-127Article in journal (Refereed)
    Abstract [en]

    Melanoma is the deadliest form of skin cancer. Early detection of melanoma is vital, as it helps in decreasing the death rate as well as treatment costs. Dermatologists are using image-based diagnostic tools to assist them in decision-making and detecting melanoma at an early stage. We aim to develop a novel handheld medical scanning device dedicated to early detection of melanoma at the primary healthcare with low cost and high performance. However, developing this particular device is very challenging due to the complicated computations required by the embedded diagnosis system. In this paper, we propose a hardware-friendly design for implementing an embedded system by exploiting the recent hardware advances in reconfigurable computing. The developed embedded system achieved optimized implementation results for the hardware resource utilization, power consumption, detection speed and processing time with high classification accuracy rate using real data for melanoma detection. Consequently, the proposed embedded diagnosis system meets the critical embedded systems constraints, which is capable for integration towards a cost- and energy-efficient medical device for early detection of melanoma.

  • 44.
    Afshar, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lock-Based Resource Sharing for Real-Time Multiprocessors2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Embedded systems are widely used in the industry and are typically resource constrained, i.e., resources such as processors, I/O devices, shared buffers or shared memory might be limited in the system. Hence, techniques that can enable an efficient usage of processor bandwidths in such systems are of great importance. Locked-based resource sharing protocols are proposed as a solution to overcome resource limitation by allowing the available resources in the system to be safely shared. In recent years, due to a dramatic enhancement in the functionality of systems, a shift from single-core processors to multi-core processors has become inevitable from an industrial perspective to tackle the raised challenges due to increased system complexity. However, the resource sharing protocols are not fully mature for multi-core processors. The two classical multi-core processor resource sharing protocols, spin-based and suspension-based protocols, although providing mutually exclusive access to resources, can introduce long blocking delays to tasks, which may be unacceptable for many industrial applications. In this thesis we enhance the performance of resource sharing protocols for partitioned scheduling, which is the de-facto scheduling standard for industrial real-time multi-core processor systems such as in AUTOSAR, in terms of timing and memory requirements.

     

    A new scheduling approach uses a resource efficient hybrid approach combining both partitioned and global scheduling where the partitioned scheduling is used to schedule the major number of tasks in the system. In such a scheduling approach applications with critical task sets use partitioned scheduling to achieve higher level of predictability. Then the unused bandwidth on each core that is remained from partitioning is used to schedule less critical task sets using global scheduling to achieve higher system utilization. These scheduling schema however lacks a proper resource sharing protocol since the existing protocols designed for partitioned and global scheduling cannot be directly applied due to the complex hybrid structure of these scheduling frameworks. In this thesis we propose a resource sharing solution for such a complex structure. Further, we provide the blocking bounds incurred to tasks under the proposed protocols and enhance the schedulability analysis, which is an essential requirement for real-time systems, with the provided blocking bounds.

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  • 45.
    Afshar, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lock-Based Resource Sharing in Real-Time Multiprocessor Platforms2014Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Embedded systems are typically resource constrained, i.e., resources such as processors, I/O devices, shared buffers or shared memory can be limited for tasks in the system. Therefore, techniques that enable an efficient usage of such resources are of great importance.

    In the industry, typically large and complex software systems are divided into smaller parts (applications) where each part is developed independently. Migration towards multiprocessor platforms has become inevitable from an industrial perspective. Due to such migration and to efficient use of system resources, these applications eventually may be integrated on a shared multiprocessor platform. In order to facilitate the integration phase of the applications on a shared platform, the timing and resource requirements of each application can be provided in an interface when the application is developed. The system integrator can benefit from such provided information in the interface of each application to ease the integration process. In this thesis, we have provided the resource and timing requirements of each application in their interfaces for applications that may need several processors to be allocated on when they are developed.

    Although many scheduling techniques have been studied for multiprocessor systems, these techniques are usually based on the assumption that tasks are independent, i.e. do not share resources other than the processors. This assumption is typically not true. In this thesis, we provide an extension to such systems to handle sharing of resources other than processor among tasks. Two traditional approaches exist for multiprocessor systems to schedule tasks on processors. A recent scheduling approach for multiprocessors has combined the two traditional approaches and achieved a hybrid more efficient approach compared to the two previous one. Due to the complex nature of this scheduling approach the conventional approaches for resource sharing could not be used straight forwardly. In this thesis, we have modified resource sharing approaches such that they can be used in such hybrid scheduling systems. A second concern is that enabling resource sharing in the systems can cause unpredictable delays and variations in response time of tasks which can degrade system performance. Therefore, it is of great significance to improve the resource handling techniques to reduce the effect of imposed delays caused by resource sharing in a multiprocessor platform. In this thesis we have proposed alternative techniques for resource handling that can improve system performance for special setups.

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    fulltext
  • 46.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, R. J.
    Technische Universiteit Eindhoven, Eindhoven, Netherlands .
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Flexible spin-lock model for resource sharing in multiprocessor real-time systems2014In: Proc. IEEE Int. Symp. Ind. Embedded Syst., SIES, 2014, p. 41-51Conference paper (Refereed)
    Abstract [en]

    Various approaches can be utilized upon resource locking for mutually exclusive resource access in multiprocessor platforms. So far two conventional approaches exist for dealing with tasks that are blocked on a global resource in a multi-processor platform. Either the blocked task performs a busy wait, i.e. spins, at the highest priority level until the resource is released, or it is suspended. Although both approaches provide mutually exclusive access to resources, they can introduce long blocking delays to tasks, which may be unacceptable for many industrial applications. In this paper, we propose a general spin-based model for resource sharing in multiprocessor platforms in which the priority of the blocked tasks during spinning can be selected arbitrarily. Moreover, we provide the analysis for two selected spin-lock priorities and we show by means of a general comparison as well as specific examples that these solutions may provide a better performance for higher priority tasks.

  • 47.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, Reinder J.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Resource sharing in a hybrid partitioned/global scheduling framework for multiprocessors2015In: IEEE International Conference on Emerging Technologies and Factory Automation, ETFA, 2015Conference paper (Refereed)
    Abstract [en]

    For resource-constrained embedded real-time systems, resource-efficient approaches are very important. Such an approach is presented in this paper, targeting systems where a critical application is partitioned on a multi-core platform and the remaining capacity on each core is provided to a noncritical application using resource reservation techniques. To exploit the potential parallelism of the non-critical application, global scheduling is used for its constituent tasks. Previously, we enabled intra-application resource sharing for such a framework, i.e. each application has its own dedicated set of resources. In this paper, we enable inter-application resource sharing, in particular between the critical application and the non-critical application. This effectively enables resource sharing in a hybrid partitioned/global scheduling framework on multiprocessors. For resource sharing, we use a spin-based synchronization protocol. We derive blocking bounds and extend existing schedulability analysis for such a system.

  • 48.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, Reinder J.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Technische Universiteit Eindhoven, Eindhoven, Netherlands.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Resource Sharing Under Global Scheduling with Partial Processor Bandwidth2015In: 2015 10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015 - Proceedings, 2015, p. 195-206Conference paper (Refereed)
    Abstract [en]

    Resource efficient approaches are of great importance for resource constrained embedded systems. In this paper, we present an approach targeting systems where tasks of a critical application are partitioned on a multi-core platform and by using resource reservation techniques, the remaining bandwidth capacity on each core is utilized for one or a set of non-critical application(s). To provide a resource efficient solution and to exploit the potential parallelism of the extra applications on the multi-core processor, global scheduling is used to schedule the tasks of the non-critical applications. Recently a specific instantiation of such a system has been studied where tasks do not share resources other than the processor. In this paper, we enable semaphore-based resource sharing among tasks within critical and non-critical applications using a suspension-based synchronization protocol. Tasks of non-critical applications have partial access to the processor bandwidth. The paper provides the systems schedulability analysis where blocking due to resource sharing is bounded. Further, we perform experimental evaluations under balanced and unbalanced allocation of tasks of a critical application to cores.

  • 49.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    J. Bril, Reinder
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Per Processor Spin-Lock Priority for Partitioned Multiprocessor Real-Time Systems2014Report (Other academic)
    Abstract [en]

    Two traditional approaches exist for a task that is blocked on a global resource; a task either performs a non-preemptive busy wait, i.e., spins, or suspends and releases the processor. Previously, we have shown that both approaches can be viewed as spinning either at the highest priority HP or at the lowest priority on the processor LP, respectively. Based on this view, previously we have generalized a task's blocking behavioral model, as spinning at any arbitrary priority level. In this paper, we focus on a particular class of spin-lock protocols from the introduced flexible spin-lock model where spinning is performed at a priority equal to or higher than the highest local ceiling of the global resources accessed on a processor referred to as CP spin-lock approach. In this paper, we assume that all tasks of a specific processor are spinning on the same priority level. Given this class and assumption, we show that there exists a spin-lock protocol in this range that dominates the classic spin-lock protocol which tasks spin on highest priority level (HP). However we show that this new approach is incomparable with the CP spin-lock approach. Moreover, we show that there may exist an intermediate spin-lock approach between the priority used by CP spin-lock approach and the new introduced spin-lock approach that can make a task set schedulable when those two cannot. We provide an extensive evaluation results comparing the HP, CP and the new proposed approach.

  • 50.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    J. Bril, Reinder
    Technische Universiteit Eindhoven, Eindhoven, The Netherlands.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Per Processor Spin-Lock Priority for Partitioned Multiprocessor Real-Time Systems2017In: Leibniz Transactions on Embedded Systems, ISSN 2199-2002, no 2Article in journal (Other academic)
    Abstract [en]

    Two traditional approaches exist for a task that is blocked on a global resource; a task either performs a non-preemptive busy wait, i.e., spins, or suspends and releases the processor. Previously, we have shown that both approaches can be viewed as spinning either at the highest priority HP or at the lowest priority on the processor LP, respectively. Based on this view, previously we have generalized a task's blocking behavioral model, as spinning at any arbitrary priority level. In this paper, we focus on a particular class of spin-lock protocols from the introduced flexible spin-lock model where spinning is performed at a priority equal to or higher than the highest local ceiling of the global resources accessed on a processor referred to as CP spin-lock approach. In this paper, we assume that all tasks of a specific processor are spinning on the same priority level. Given this class and assumption, we show that there exists a spin-lock protocol in this range that dominates the classic spin-lock protocol which tasks spin on highest priority level (HP). However we show that this new approach is incomparable with the CP spin-lock approach. Moreover, we show that there may exist an intermediate spin-lock approach between the priority used by CP spin-lock approach and the new introduced spin-lock approach that can make a task set schedulable when those two cannot. We provide an extensive evaluation results comparing the HP, CP and the new proposed approach.

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