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  • 1.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, Luis
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. University of Porto, Porto, Portugal .
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    MTU Configuration for Real-Time Switched Ethernet Networks2016In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 70, p. 15-25Article in journal (Refereed)
    Abstract [en]

    In this paper, we show that in real-time switched Ethernet networks reducing the Maximum Transmission Unit (MTU) size may cause an increase or decrease in the response time of messages. This contradicting behavior arises an optimization problem for configuring the MTU size. We formulate the optimization problem in the context of the multi-hop HaRTES architecture, which is a hard real-time Ethernet protocol. As part of the solution, we propose a search-based algorithm to achieve optimum solutions. We modify the algorithm by presenting two techniques to reduce the search space. Then, we propose a heuristic algorithm with a pseudo-polynomial time complexity based on the search-based algorithm. We perform several experiments, and we show that the proposed heuristic results in an improvement regarding messages response times, compared with configuring the MTU to the maximum or minimum values. Moreover, we show in small network configurations that the heuristic performs as good as the search-based algorithm in many cases.

  • 2.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Malardalen Univ, Malardalen Real Time Res Ctr MRTC, POB 883, SE-72123 Vasteras, Sweden..
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Malardalen Univ, Malardalen Real Time Res Ctr MRTC, POB 883, SE-72123 Vasteras, Sweden..
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Malardalen Univ, Malardalen Real Time Res Ctr MRTC, POB 883, SE-72123 Vasteras, Sweden..
    SEtSim: A modular simulation tool for switched Ethernet networks2016In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 65, p. 1-14Article in journal (Refereed)
    Abstract [en]

    Using high bandwidth network technologies in real-time applications, for example in automotive systems, is rapidly increasing. In this context, switched Ethernet-based protocols are becoming more popular due to their features such as providing a collision-free domain for transmission of messages. Moreover, switched Ethernet is a mature technology. Several protocols based on switched Ethernet have been proposed over the years, tuned for time critical applications. However, research for improving the features and performance of these protocols is still on-going. In order to evaluate the performance of early stage proposed protocols, the mathematical analysis and/or experiments are required. However, performing an experiment for complex network topologies with a large set of messages is not effortless. Therefore, using a simulation based approach for evaluating a protocol's performance and/or properties is highly useful. As a response to this we have developed a simulator, called SEtSim, for switched Ethernet networks. SEtSim is developed based on Simulink, and it currently supports different network topologies of the FIT-SE protocol as well as Ethernet AVB protocol. However, the kernel of SEtSim is designed such that it is possible to add and integrate other switched Ethernet-based protocols. In this paper, we describe the design of SEtSim and we show its scalability.

  • 3.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Robert Bosch GmbH, Renningen, Germany.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Arcticus Systems AB, Järfälla, Sweden.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    End-to-End Timing Analysis of Cause-Effect Chains in Automotive Embedded Systems2017In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 80, no Supplement C, p. 104-113Article in journal (Refereed)
    Abstract [en]

    Automotive embedded systems are subjected to stringent timing requirements that need to be verified. One of the most complex timing requirement in these systems is the data age constraint. This constraint is specified on cause- effect chains and restricts the maximum time for the propagation of data through the chain. Tasks in a cause-effect chain can have different activation patterns and different periods, that introduce over- and under-sampling effects, which additionally aggravate the end-to-end timing analysis of the chain. Furthermore, the level of timing information available at various development stages (from modeling of the software architecture to the software implementation) varies a lot, the complete timing information is available only at the implementation stage. This uncertainty and limited timing information can restrict the end-to-end timing analysis of these chains. In this paper, we present methods to compute end-to-end delays based on different levels of system information. The characteristics of different communication semantics are further taken into account, thereby enabling timing analysis throughout the development process of such heterogeneous software systems. The presented methods are evaluated with extensive experiments. As a proof of concept, an industrial case study demonstrates the applicability of the proposed methods following a state-of-the-practice development process.

  • 4.
    Betts, Adam
    et al.
    Mälardalen University, School of Health, Care and Social Welfare.
    Bernat, Guillem
    Rapita Syst Ltd, IT Ctr, York, England.
    Identifying irreducible loops in the Instrumentation Point Graph2011In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 57, no 7, p. 720-733Article in journal (Refereed)
    Abstract [en]

    The Instrumentation Point Graph (IPG) is a program model whose primary usage is within hybrid measurement-based frameworks that compute Worst-Case Execution Time (WCET) estimates. The IPG represents the transitions between instrumentation points (Ipoints) that are inserted into the program to collect measurements at run time. However, uncontrolled Ipoint placement often causes the resultant IPG to contain unstructured (i.e. irreducible) loops, potentially compromising the safety of WCET estimates unless the hierarchical containment among IPG loops can be correctly identified. The contributions of this paper are fourfold: (1) we show that the IPG is more susceptible to irreducibility even when the program itself is well structured; (2) we demonstrate that state-of-the-art loop detection algorithms, designed specifically to handle irreducible loops, generally fail to construct the correct hierarchical relationship between IPG loops; (3) we present an algorithm that identifies arbitrary irreducible loops in the IPG during its construction from another graph-based model, an extended type of Control Flow Graph (CFG) called the CFG(+); (4) we show how the structural relation between the IPG and the CFG(+) allows loop bounds obtained through static analysis to be transferred onto the IPG. (C) 2011 Elsevier B.V. All rights reserved.

  • 5.
    Bygde, Stefan
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Ermedahl, Andreas
    Mälardalen University, School of Innovation, Design and Engineering.
    Lisper, Björn
    Mälardalen University, School of Innovation, Design and Engineering.
    An efficient algorithm for parametric WCET calculation2011In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 57, no 6, p. 614-624Article in journal (Refereed)
    Abstract [en]

    Static WCET analysis is a process dedicated to derive a safe upper bound of the worst-case execution time of a program. In many real-time systems, however, a constant global WCET estimate is not always so useful since a program may behave very differently depending on its configuration or mode. A parametric WCET analysis derives the upper bound as a formula rather than a constant. This paper presents a new algorithm that can obtain a safe parametric estimate of the WCET of a program. This algorithm is evaluated on a large set of benchmarks and compared to a previous approach to parametric WCET calculation. The evaluation shows that the new algorithm, to the cost of some imprecision, scales much better and can handle more realistic programs than the previous approach.

  • 6.
    Corredor, Iván
    et al.
    Technical University of Madrid.
    Martínez-Ortega, José-Fernán
    Technical University of Madrid.
    Familiar, Miguel S
    Technical University of Madrid.
    Bringing pervasive embedded networks to the service cloud: A lightweight middleware approach2011In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 57, no 10, p. 916-933Article in journal (Refereed)
    Abstract [en]

    The emergence of novel pervasive networks that consist of tiny embedded nodes have reduced the gap between real and virtual worlds. This paradigm has opened the Service Cloud to a variety of wireless devices especially those with sensorial and actuating capabilities. Those pervasive networks contribute to build new context-aware applications that interpret the state of the physical world at real-time. However, traditional Service-Oriented Architectures (SOA), which are widely used in the current Internet are unsuitable for such resource-constraint devices since they are too heavy. In this research paper, an internetworking approach is proposed in order to address that important issue. The main part of our proposal is the Knowledge-Aware and Service-Oriented (KASO) Middleware that has been designed for pervasive embedded networks. KASO Middleware implements a diversity of mechanisms, services and protocols which enable developers and business processing designers to deploy, expose, discover, compose, and orchestrate real-world services (i.e. services running on sensor/actuator devices). Moreover, KASO Middleware implements endpoints to offer those services to the Cloud in a REST manner. Our internetworking approach has been validated through a real healthcare telemonitoring system deployed in a sanatorium. The validation tests show that KASO Middleware successfully brings pervasive embedded networks to the Service Cloud.

  • 7.
    Crnkovic, Ivica
    et al.
    Mälardalen University, School of Innovation, Design and Engineering. Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Stafford, Judith
    Embedded Systems Software Architecture2013In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 59, no 10, Part D, p. 1013-1014Article in journal (Refereed)
    Abstract [en]

    Embedded Systems are the dominate type of computer systems today; they span a range from small systems that include a simple platform integrated with sensors and actuators, to large distributed systems consisting of hundreds, or possibly thousand, intensely interactive nodes. In recent years Software has become the most important part of Embedded Systems – it implements the complex system functionality, is a currier of the system integration, and it is enabler of important extra-functional system properties. In many aspects, software for Embedded Systems has reached functional complexity of general-purpose software but faces severe constraints. This special issue includes six research papers that address some of the mentioned challenges.

  • 8.
    Ermedahl, Andreas
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Puschner, Peter
    Vienna University of Technology.
    Preface to the special issue on worst-case execution-time analysis2011In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 57, no 7, p. 675-676Article in journal (Other academic)
  • 9.
    Holenderski, Mike J.
    et al.
    Eindhoven University of Technology, Netherlands .
    Bril, Reinder J.
    Eindhoven University of Technology, Netherlands .
    Lukkien, Johan
    Eindhoven University of Technology, Netherlands .
    Grasp: Visualizing the Behavior of Hierarchical Multiprocessor Real-Time Systems2013In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 59, no 6, p. 307-314Article in journal (Refereed)
    Abstract [en]

    Trace visualization is a viable approach for gaining insight into the behavior of complex distributed realtime systems. Grasp is a versatile trace visualization toolset. Its flexible plugin infrastructure allows for easy extension with custom visualization and analysis techniques for automatic trace verification. This paper presents its visualization capabilities for hierarchical multiprocessor systems, including partitioned and global multiprocessor scheduling with migrating tasks and jobs, communication between jobs via shared memory and message passing, and hierarchical scheduling in combination with multiprocessor scheduling. For tracing distributed systems with asynchronous local clocks Grasp also supports the synchronization of traces from different processors during the visualization and analysis.

  • 10.
    Mubeen, Saad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Mäki-Turja, Jukka
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Communications-oriented development of component-based vehicular distributed real-time embedded systems2014In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 60, no 2, p. 207-220Article in journal (Refereed)
    Abstract [en]

    We propose a novel model- and component-based technique to support communications-oriented development of software for vehicular distributed real-time embedded systems. The proposed technique supports modeling of legacy nodes and communication protocols by encapsulating and abstracting the internal implementation details and protocols. It also allows modeling and performing timing analysis of the applications that contain network traffic originating from outside of the system such as vehicle-to-vehicle, vehicle-to-infrastructure, and cloud-based applications. Furthermore, we present a method to extract end-to-end timing models to support end-to-end timing analysis. We also discuss and solve the issues involved during the extraction of these models. As a proof of concept, we implement our technique in the Rubus Component Model which is used for the development of software for vehicular embedded systems by several international companies. We also conduct an application-case study to validate our approach.

  • 11.
    Mubeen, Saad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Mäki-Turja, Jukka
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    MPS-CAN Analyzer: Integrated Implementation of Response-Time Analyses for Controller Area Network2014In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 60, no 10, p. 828-841Article in journal (Refereed)
    Abstract [en]

    We present a new response-time analyzer for Controller Area Network (CAN) that integrates and implements a number of response-time analyses which address various transmission modes and practical limitations in the CAN controllers. The existing tools for the response-time analysis of CAN support only periodic and sporadic messages. They do not analyze mixed messages which are partly periodic and partly sporadic. These messages are implemented by several higher-level protocols based on CAN that are used in the automotive industry. The new analyzer supports periodic, sporadic as well as mixed messages. It can analyze the systems where periodic and mixed messages are scheduled with offsets. It also supports the analysis of all types of messages while taking into account several queueing policies and buffer limitations in the CAN controllers such as abortable or non-abortable transmit buffers. Moreover, the tool supports the analysis of mixed, periodic and sporadic messages in the heterogeneous systems where Electronic Control Units (ECUs) implement different types of queueing policies and have different types of buffer limitations in the CAN controllers. We conduct a case study of a heterogeneous application from the automotive domain to show the usability of the tool. Moreover, we perform a detailed evaluation of the implemented analyses.

  • 12.
    Niazi, M. F.
    et al.
    Turku Centre for Computer Science, Turku, Finland .
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Tenhunen, H.
    Turku Centre for Computer Science, Turku, Finland .
    A development and verification framework for the SegBus platform2013In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 59, no 10 PART C, p. 1015-1031Article in journal (Refereed)
    Abstract [en]

    We describe the creation of a development framework for a platform-based design approach, in the context of the SegBus platform. The work intends to provide automated procedures for platform build-up and application mapping. The solution is based on a model-based process and heavily employs the UML. We develop a Domain Specific Language to support the platform modeling. An emulator is consequently introduced to allow an as much as possible accurate performance estimation of the solution, at high abstraction levels. Automated execution schedule generation is also featured. The resulting framework is applied to build actual design solutions for a MP3-decoder application. 

  • 13.
    Sapienza, Gaetana
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Brestovac, Goran
    Grgurina, Robi
    Seceleanu, Tiberiu
    Mälardalen University, School of Innovation, Design and Engineering.
    Assessing Multiple Criteria Decision Analysis Suitability for HW/SW Deployment in Embedded Systems DesignIn: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165Article in journal (Refereed)
  • 14.
    Terraneo, F.
    et al.
    Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy.
    Papadopoulos, Alessandro
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Leva, A.
    Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy.
    Prandini, M.
    Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy.
    FLOPSYNC-QACS: Quantization-aware clock synchronization for wireless sensor networks2017In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 80, p. 77-84Article in journal (Refereed)
    Abstract [en]

    Distributed real-time systems often rely on clock synchronization. However, the achievement of precise synchronization in Wireless Sensor Networks (WSNs) is hampered by competing design challenges, which finally causes many WSN hardware platforms to rely on low frequency clock crystal for local timebase provision. Although this solution is inexpensive and with a remarkably low energy consumption, it limits the resolution at which time can be measured. The FLOPSYNC synchronization scheme was then introduced to compensate for possible quartz crystal imperfections. The main limitation of FLOPSYNC is that it does not account for the effects of quantization. In this paper we propose a switched control variant of the base FLOPSYNC scheme to address quantization explicitly in the compensator design, providing clock synchronization in cost-sensitive WSN node platforms with a minimal additional overhead. Experimental evidence is given that the approach reaches a synchronization error of at most 1 clock tick in a real WSN.

  • 15.
    Yin, Hang
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Mode switch timing analysis for component-based multi-mode systems2013In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 59, no 10, p. 1299-1318Article in journal (Refereed)
    Abstract [en]

    The growing complexity of embedded systems software requires new techniques for their development. A common approach to reducing software complexity is to partition system behavior into different operational modes. Such a multi-mode system can change its behavior by switching between modes under certain circumstances. Another approach to simplifying software development is Component-Based Software Engineering, which allows a system to be developed by reusable components. Combining both approaches, we get component-based development of multi-mode systems, for which a key issue is the mode switch handling. Since most existing mode switch techniques do not consider component-based systems, we present in this article an approach—the Mode Switch Logic (MSL)—for the development of component-based multi-mode systems. Additionally, we provide a timing analysis for the mode switch of systems using our MSL. Finally, the fundamentals of MSL and its mode switch timing analysis are demonstrated and evaluated by a case study, an Adaptive Cruise Control system.

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