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  • 1.
    Abbaspour Asadollah, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Concurrency Bugs: Characterization, Debugging and Runtime Verification2018Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Concurrent software has been increasingly adopted in recent years, mainly due to the introduction of multicore platforms. However, concurrency bugs are still difficult to test and debug due to their complex interactions involving multiple threads (or tasks). Typically, real world concurrent software has huge state spaces. Thus, testing techniques and handling of concurrency bugs need to focus on exposing the bugs in this large space. However, existing solutions typically do not provide debugging information to developers (and testers) for understanding the bugs.

    Our work focuses on improving concurrent software reliability via three contributions: 1) An investigation of concurrent software challenges with the aim to help developers (and testers) to better understand concurrency bugs. We propose a classification of concurrency bugs and discuss observable properties of each type of bug. In addition, we identify a number of gaps in the body of knowledge on concurrent software bugs and their debugging. 2) Exploring concurrency related bugs in real-world software with respect to the reproducibility of bugs, severity of their consequence and effort required to fix them. Our findings here is that concurrency bugs are different from other bugs in terms of their fixing time and severity, while they are similar in terms of reproducibility. 3) A model for monitoring concurrency bugs and the implementation and evaluation of a related runtime verification tool to detect the bugs. In general, runtime verification techniques are used to (a) dynamically verify that the observed behaviour matches specified properties and (b) explicitly recognize understandable behaviors in the considered software. Our implemented tool is used to detect concurrency bugs in embedded software and is in its current form tailored for the FreeRTOS operating system. It helps developers and testers to automatically identify concurrency bugs and subsequently helps to reduce their finding and fixing time.

  • 2.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Daniel, Sundmark
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Eldh, S.
    Ericsson AB, Kista, Sweden.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Runtime Verification Tool for Detecting Concurrency Bugs in FreeRTOS Embedded Software2018In: Proceedings - 17th International Symposium on Parallel and Distributed Computing, ISPDC 2018, Institute of Electrical and Electronics Engineers Inc. , 2018, p. 172-179, article id 8452035Conference paper (Refereed)
    Abstract [en]

    This article presents a runtime verification tool for embedded software executing under the open source real-time operating system FreeRTOS. The tool detects and diagnoses concurrency bugs such as deadlock, starvation, and suspension based-locking. The tool finds concurrency bugs at runtime without debugging and tracing the source code. The tool uses the Tracealyzer tool for logging relevant events. Analysing the logs, our tool can detect the concurrency bugs by applying algorithms for diagnosing each concurrency bug type individually. In this paper, we present the implementation of the tool, as well as its functional architecture, together with illustration of its use. The tool can be used during program testing to gain interesting information about embedded software executions. We present initial results of running the tool on some classical bug examples running on an AVR 32-bit board SAM4S. 

  • 3.
    Afshar, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lock-Based Resource Sharing for Real-Time Multiprocessors2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Embedded systems are widely used in the industry and are typically resource constrained, i.e., resources such as processors, I/O devices, shared buffers or shared memory might be limited in the system. Hence, techniques that can enable an efficient usage of processor bandwidths in such systems are of great importance. Locked-based resource sharing protocols are proposed as a solution to overcome resource limitation by allowing the available resources in the system to be safely shared. In recent years, due to a dramatic enhancement in the functionality of systems, a shift from single-core processors to multi-core processors has become inevitable from an industrial perspective to tackle the raised challenges due to increased system complexity. However, the resource sharing protocols are not fully mature for multi-core processors. The two classical multi-core processor resource sharing protocols, spin-based and suspension-based protocols, although providing mutually exclusive access to resources, can introduce long blocking delays to tasks, which may be unacceptable for many industrial applications. In this thesis we enhance the performance of resource sharing protocols for partitioned scheduling, which is the de-facto scheduling standard for industrial real-time multi-core processor systems such as in AUTOSAR, in terms of timing and memory requirements.

     

    A new scheduling approach uses a resource efficient hybrid approach combining both partitioned and global scheduling where the partitioned scheduling is used to schedule the major number of tasks in the system. In such a scheduling approach applications with critical task sets use partitioned scheduling to achieve higher level of predictability. Then the unused bandwidth on each core that is remained from partitioning is used to schedule less critical task sets using global scheduling to achieve higher system utilization. These scheduling schema however lacks a proper resource sharing protocol since the existing protocols designed for partitioned and global scheduling cannot be directly applied due to the complex hybrid structure of these scheduling frameworks. In this thesis we propose a resource sharing solution for such a complex structure. Further, we provide the blocking bounds incurred to tasks under the proposed protocols and enhance the schedulability analysis, which is an essential requirement for real-time systems, with the provided blocking bounds.

  • 4.
    Agha Jafari Wolde, Bahareh
    Mälardalen University, School of Innovation, Design and Engineering.
    A systematic Mapping study of ADAS and Autonomous Driving2019Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Nowadays, autonomous driving revolution is getting closer to reality. To achieve the Autonomous driving the first step is to develop the Advanced Driver Assistance System (ADAS). Driver-assistance systems are one of the fastest-growing segments in automotive electronics since already there are many forms of ADAS available. To investigate state of art of development of ADAS towards Autonomous Driving, we develop Systematic Mapping Study (SMS). SMS methodology is used to collect, classify, and analyze the relevant publications. A classification is introduced based on the developments carried out in ADAS towards Autonomous driving. According to SMS methodology, we identified 894 relevant publications about ADAS and its developmental journey toward Autonomous Driving completed from 2012 to 2016. We classify the area of our research under three classifications: technical classifications, research types and research contributions. The related publications are classified under thirty-three technical classifications. This thesis sheds light on a better understanding of the achievements and shortcomings in this area. By evaluating collected results, we answer our seven research questions. The result specifies that most of the publications belong to the Models and Solution Proposal from the research type and contribution. The least number of the publications belong to the Automated…Autonomous driving from the technical classification which indicated the lack of publications in this area. 

  • 5.
    Ahlberg, Carl
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Leon, Miguel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ekstrand, Fredrik
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ekström, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    The Genetic Algorithm Census TransformManuscript (preprint) (Other academic)
  • 6.
    Akbari, N.
    et al.
    University of Tehran, Tehran, Iran.
    Modarressi, M.
    University of Tehran, Tehran, Iran.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Royal Institute of Technology (KTH), Sweden.
    Loni, Mohammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Royal Institute of Technology (KTH), Sweden.
    A Customized Processing-in-Memory Architecture for Biological Sequence Alignment2018In: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, Institute of Electrical and Electronics Engineers Inc. , 2018, article id 8445124Conference paper (Refereed)
    Abstract [en]

    Sequence alignment is the most widely used operation in bioinformatics. With the exponential growth of the biological sequence databases, searching a database to find the optimal alignment for a query sequence (that can be at the order of hundreds of millions of characters long) would require excessive processing power and memory bandwidth. Sequence alignment algorithms can potentially benefit from the processing power of massive parallel processors due their simple arithmetic operations, coupled with the inherent fine-grained and coarse-grained parallelism that they exhibit. However, the limited memory bandwidth in conventional computing systems prevents exploiting the maximum achievable speedup. In this paper, we propose a processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications. The design is composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture. Experimental results show that the proposed architecture results in up to 2.4x speedup and 41% reduction in power consumption, compared to a processor-side parallel implementation. 

  • 7.
    Alexander, Karlsson
    Mälardalen University, School of Innovation, Design and Engineering.
    Design and Development of a Wireless Multipoint E-stop System for Autonomous Haulers2018Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Safety-related functions are important in autonomous industrial applications and are featured in an extensive body of work contained within the standards. The implementation of safety-related systems is commonly done by an external company at a great cost and with limited flexibility. Thus, the objective of this thesis was to develop and implement a safety-related system using o-the-shelf products and to analyse how well it can comply with the established standards of safety-related functions. This work has sought to review the current standards for safety-functions, the eectsof harsh radio environments on safety-related systems, and how to validate the safety-function.The system development process was used to gain knowledge by rst building the concept based on pre-study. After the pre-study was nished, the process moved to the development of software, designed to maintain a wireless heartbeat as well as to prevent collisions between the autonomous and manual-driven vehicles at a quarry, and implementation of the system in real hardware. Finally, a set of software (simulations) and hardware (measurements in an open-pit mine) tests were performed to test the functionality of the system. The wireless tests showed that the system adhered to the functional requirements set by the company, however, the evaluated performance level according to ISO 13849-1 resulted in performance level B which is insucient for a safety-related function. This work demonstrates that it is not possible to develop a safety-related system using the off-the-shelf products chosen, without hardware redundancy.

  • 8.
    Andersson, Martin
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjöström, Emil
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    COMPARISON OF TIME- AND EVENT-TRIGGERED STRATEGIES FOR WIRELESS COMMUNICATION IN EMBEDDED SYSTEMS: Design of a lab assignment for university level course on data communication in embedded systems2016Independent thesis Basic level (degree of Bachelor), 180 HE creditsStudent thesis
    Abstract [en]

    Embedded systems (ESs) and wireless technologies are in constant rapid development and therefore it is important to educate people in these subjects. This thesis work has the goal of developing a lab assignment for a university level course on data communication in embedded systems. Embedded systems have reliability and timeliness requirements that have to be fulfilled. These criteria pose problems to be addressed while ESs are used in conjunction with communication over wireless medium, which has some underlying limitations. These limitations come in the form of interference, degradation of signal strength with the distance and possible unwanted delays. This thesis work starts with a literature study on medium access control (MAC) methods and their possibilities for adoption of time-triggered and event-driven strategies for ESs with time constraints and continues with the lab assignment design, implementation and testing. Taking into account timing requirements brought by ESs and the specifics of the lab, i.e., limited time given to the students to solve the problem and compulsory usage of available lab equipment, a design with two communicating raspberry Pis was proposed. The system consists of a sensor node sending its readings to a controller, which is responsible for analyzing the data and actuating a set of LED lights as a response to the input data. The communication is done over a WiFi network and three different programs, organizing the communication in time-triggered, eventdriven or a combination of the two fashions are developed. Each program is tested under three environmental conditions and the results from these tests clearly show the limitation of the underlying CSMA/CA MAC adopted in WiFi and give a greater understanding of the advantages and disadvantages of different strategies for communication design.

  • 9.
    Asadi, Nima
    Mälardalen University, School of Innovation, Design and Engineering.
    Enhancing the Monitoring of Real-Time Performance in Linux2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    There is a growing trend in applying Linux operating system in the domain of embeddedsystems. This is due to the important features that Linux benets from, such as beingopen source, its light weight compared to other major operating systems, its adaptabilityto dierent platforms, and its more stable performance speed. However, there are up-grades that still need to be done in order to use Linux for real-time purposes. A numberof dierent approaches have been suggested in order to improve Linux's performance inreal-time environment. Nevertheless, proposing a correct-by-construction system is verydicult in real-time environment, mainly due to the complexity and unpredictability ofthem. Thus, run-time monitoring can be a helpful approach in order to provide the userwith data regarding to the actual timing behavior of the system which can be used foranalysis and modication of it. In this thesis work, a design for run-time monitoringis suggested and implemented on a real-time scheduler module that assists Linux withreal-time tasks. Besides providing crucial data regarding the timing performance of thesystem, this monitor predicts violations of timing requirements based on the currenttrace of the system performance.

  • 10.
    Ashjaei, Mohammad
    Mälardalen University, School of Innovation, Design and Engineering. Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Multi-Hop Real-Time Communication over Switched Ethernet Technology2014Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Switched Ethernet technology has been introduced to be exploited in real-time communication systems due to its features such as its high throughput and wide availability, hence being a cost-effective solution. Many real-time switched Ethernet protocols have been developed, preserving the profits of traditional Ethernet technology, to overcome the limitations imposed by using commercially available (COTS) switches. These limitations mainly originate from the non-deterministic behavior of the Ethernet switches inherent in the use of FIFO queues and a limited number of priority levels.

     

    In our research we focus on two particular real-time communication technologies, one based on COTS Ethernet switches named the FTT-SE architecture and the other using a modified Ethernet switch called the HaRTES architecture. Both architectures are based on a master-slave technique supporting different and temporally isolated traffic types including real-time periodic, real-time sporadic and non-real-time traffic. Also, they provide mechanisms implementing adaptivity as a response to the requirements imposed by dynamic real-time applications. Nevertheless, the two mentioned architectures were originally developed for a simple network consisting of a single switch, and they were lacking support for multi-hop communication. In industrial applications, multi-hop communication is essential as the networks comprise a high number of nodes, that is far beyond the capability of a single switch.

     

    In this thesis, we study the challenges of building multi-hop communication using the FTT-SE and the HaRTES architectures. We propose different architectures to provide multi-hop communication while preserving the key characteristics of the single-switch architecture such as timeliness guarantee, resource efficiency, adaptivity and dynamicity. We develop a response time analysis for each proposed architecture and we compare them to assess their corresponding benefits and limitations. Further, we develop a simulation tool to evaluate the solutions.

  • 11.
    Ashjaei, Mohammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Real-Time Communication over Switched Ethernet with Resource Reservation2016Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Due to the need for advanced computer-controlled functionality in distributed embedded systems the requirements on network communication are becoming overly intricate. This dissertation targets the requirements that are concerned with real-time guarantees, run-time adaptation, resource utilization and flexibility during the development. The Flexible Time-Triggered Switched Ethernet (FTT-SE) and Hard Real-Time Ethernet Switching (HaRTES) network architectures have emerged as two promising solutions that can cater for these requirements. However, these architectures do not support multi-hop communication as they are originally developed for single-switch networks. This dissertation presents a fundamental contribution in multi-hop real-time communication over the FTT-SE and HaRTES architectures targeting the above mentioned requirements. It proposes and evaluates various solutions for scheduling and forwarding the traffic through multiple switches in these architectures. These solutions preserve the ability of dynamic adaptation without jeopardizing real-time properties of the architectures. Moreover, the dissertation presents schedulability analyses for the timeliness verification and evaluation of the proposed solutions as well as several protocols to support run-time adaptation in the multi-hop communication. Finally, the work led to an end-to-end resource reservation framework, based on the proposed multi-hop architectures, to support flexibility during the development of the systems. The efficiency of the proposed solutions is evaluated on various case studies that are inspired from industrial systems.

  • 12.
    Ashjaei, Mohammad
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    End-to-end Resource Reservation Model2016Manuscript (preprint) (Other academic)
  • 13.
    Asplund, Lars
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Lundqvist, Kristina
    Mälardalen University, School of Innovation, Design and Engineering.
    Safety Critical Systems Based on Formal Models2000In: ACM SIGAda Letters, ISSN 1094-3641, Vol. XX, no 4, p. 32-39Article in journal (Refereed)
    Abstract [en]

    The Ravenscar profile for high integrity systems using Ada 95 is well defined in all real-time aspects. The complexity of the run-time system has been reduced to allow full utilization of formal methods for applications using the Ravenscar profile. In the Mana project a tool set is being developed including a formal model of a Ravenscar compliant run-time system, a gnat compatible run-time system, and an ASIS based tool to allow for the verification of a system including both COTS and code that is reused.

  • 14.
    Azhar, Muhammad
    Mälardalen University, School of Innovation, Design and Engineering.
    A Stochastic Analysis Framework for Real-Time Systems under Preemptive Priority-Driven Scheduling2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis work describes how to apply the stochastic analysis framework, presented in [1] for general priority-driven periodic real-time systems. The proposed framework is applicable to compute the response time distribution, the worst-case response time, and the deadline miss probability of the task under analysis in the fixed-priority driven scheduling system. To be specific, we modeled the task execution time by using the beta distribution. Moreover, we have evaluated the existing stochastic framework on a wide range of periodic systems with the help of defined evaluation parameters.

    In addition we have refined the notations used in system model and also developed new mathematics in order to facilitate the understanding with the concept. We have also introduced new concepts to obtain and validate the exact probabilistic task response time distribution.   

    Another contribution of this thesis is that we have extended the existing system model in order to deal with stochastic release time of a job. Moreover, a new algorithm is developed and validated using our extended framework where the stochastic dependencies exist due to stochastic release time patterns.

  • 15.
    Bakhshi Valojerdi, Zeinab
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Rodriguez-Navas, Guillermo
    Nokia Bell Labs, Israel.
    A Preliminary Roadmap for Dependability Research in Fog Computing2019Conference paper (Refereed)
    Abstract [en]

    Fog computing aims to support novel real-time applications byextending cloud resources to the network edge. This technologyis highly heterogeneous and comprises a wide variety of devicesinterconnected through the so-called fog layer. Compared to tra-ditional cloud infrastructure, fog presents more varied reliabilitychallenges, due to its constrained resources and mobility of nodes.This paper summarizes current research efforts on fault toleranceand dependability in fog computing and identifies less investigatedopen problems, which constitute interesting research directions tomake fogs more dependable.

  • 16.
    Bakhshi Valojerdi, Zeinab
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Rodriguez-Navas, Guillermo
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dependable Fog Computing: A Systematic Literature Review2019Conference paper (Refereed)
    Abstract [en]

    Fog computing has been recently introduced to bridge the gap between cloud resources and the network edge. Fog enables low latency and location awareness, which is considered instrumental for the realization of IoT, but also faces reliability and dependability issues due to node mobility and resource constraints. This paper focuses on the latter, and surveys the state of the art concerning dependability and fog computing, by means of a systematic literature review. Our findings show the growing interest in the topic but the relative immaturity of the technology, without any leading research group. Two problems have attracted special interest: guaranteeing reliable data storage/collection in systems with unreliable and untrusted nodes, and guaranteeing efficient task allocation in the presence of varying computing load. Redundancy-based techniques, both static and dynamic, dominate the architectures of such systems. Reliability, availability and QoS are the most important dependability requirements for fog, whereas aspects such as safety and security, and their important interplay, have not been investigated in depth.

  • 17.
    Bankarusamy, Sudhangathan
    Mälardalen University, School of Innovation, Design and Engineering.
    Towards hardware accelerated rectification of high speed stereo image streams2017Independent thesis Advanced level (degree of Master (Two Years)), 80 credits / 120 HE creditsStudent thesis
    Abstract [en]

    The process of combining two views of a scene in order to obtain depth information is called stereo vision. When the same is done using a computer it is then called computer stereo vision. Stereo vision is used in robotic application where depth of an object plays a role. Two cameras mounted on a rig is called a stereo camera system. Such a system is able to capture two views and enable robotic application to use the depth information to complete tasks. Anomalies are bound to occur in such a stereo rig, when both the cameras are not parallel to each other. Mounting of the cameras on a rig accurately has physical alignment limitations. Images taken from such a rig has inaccurate depth information and has to be rectified. Therefore rectification is a pre-requisite to computer stereo vision. One such a stereo rig used in this thesis is the GIMME2 stereo camera system. The system has two 10 mega-pixel cameras with on-board FPGA, RAM, processor running Linux operating system, multiple Ethernet ports and an SD card feature amongst others. Stereo rectification on memory constrained hardware is a challenging task as the process itself requires both the images to be stored in the memory. The FPGA on the GIMME2 systems must be used in order to achieve the best possible speed. Programming a system that does not have a display and for used for a specific purpose is called embedded programming. The purpose of this system is distance estimation and working with such a system falls in the Embedded Systems program. This thesis presents a method that makes rectification a step ahead for this particular system. The functionality of the algorithm is shown in MATLAB and using VHDL and is compared to available tools and systems.

  • 18.
    Baumgart, Stephan
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Volvo Construction Equipment.
    Incorporating Functional Safety in Model-based Development of Product Lines2016Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Product lines in industry are often based on an engineer’s focus on fast and feasible product instantiation rather than a precise product line development method and process as described in literature. When considering functional safety, we need a precise model that includes evidence for the safety of each variant of the product.Functional safety standards provide guidance to develop safety critical products and require that evidence is collected to prove the safety of the product. But today’s functional safety standards do not provide guidance on how to achieve functional safety in product lines. At the same time arguments need to be collected during development so that each product configuration is safe and is fulfilling the requirements of the standards. Providing these arguments requires tracing safety-related requirements and dependencies through the development process taking the impact of variability in different development artifacts into consideration.

    In this thesis, we study the challenges of developing safety critical products in product lines. We explore industrial practices to achieve functional safety standard compliance in product lines by interviewing practitioners from different companies and by collecting the reported challenges and practices. This information helps us to identify improvement areas and we derive requirements that a product line engineering method needs to fulfill. Based on these findings we analyze variability management methods from the software product line engineering research domain to identify potential candidate solutions that can be adapted to support safety critical products. We provide an approach for capturing functional safety related characteristics in a model-based product line engineering method. We apply our method in an industrial case demonstrating the applicability.

  • 19.
    Becker, Matthias
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Consolidating Automotive Real-Time Applications on Many-Core Platforms2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Automotive systems have transitioned from basic transportation utilities to sophisticated systems. The rapid increase in functionality comes along with a steep increase in software complexity. This manifests itself in a surge of the number of functionalities as well as the complexity of existing functions. To cope with this transition, current trends shift away from today’s distributed architectures towards integrated architectures, where previously distributed functionality is consolidated on fewer, more powerful, computers. This can ease the integration process, reduce the hardware complexity, and ultimately save costs.

    One promising hardware platform for these powerful embedded computers is the many-core processor. A many-core processor hosts a vast number of compute cores, that are partitioned on tiles which are connected by a Network-on-Chip. These natural partitions can provide exclusive execution spaces for different applications, since most resources are not shared among them. Hence, natural building blocks towards temporally and spatially separated execution spaces exist as a result of the hardware architecture.

    Additionally to the traditional task local deadlines, automotive applications are often subject to timing constraints on the data propagation through a chain of semantically related tasks. Such requirements pose challenges to the system designer as they are only able to verify them after the system synthesis (i.e. very late in the design process).

    In this thesis, we present methods that transform complex timing constraints on the data propagation delay to precedence constraints between individual jobs. An execution framework for the cluster of the many-core is proposed that allows access to cluster external memory while it avoids contention on shared resources by design. A partitioning and configuration of the Network-on-Chip provides isolation between the different applications and reduces the access time from the clusters to external memory. Moreover, methods that facilitate the verification of data propagation delays in each development step are provided. 

  • 20.
    Becker, Matthias
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Efficient Resource Management for Many-Core based Industrial Real-Time Systems2015Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    The increased complexity of today’s industrial embedded systems stands inneed for more computational power while most systems must adhere to a restrictedenergy consumption, either to prolong the battery lifetime or to reduceoperational costs. The many-core processor is therefore a natural fit. Due tothe simple architecture of the compute cores, and therefore their good analyzability,such processors are additionally well suited for real-time applications.In our research, we focus on two particular problems which need to be addressedin order to pave the way into the many-core era. The first area is powerand thermal aware execution frameworks, where we present different energyaware extensions to well known load balancing algorithms, allowing them todynamically scale the number of active cores depending on their workload.In contrast, an additional framework is presented which balances workloadsto minimize temperature gradients on the die. The second line of works focuseson industrial standards in the face of massively parallel platforms, wherewe address the automotive and automation domain. We present an executionframework for IEC 61131-3 applications, allowing the consolidation of severalIEC 61131-3 applications on the same platform. Additionally, we discussseveral architectural options for the AUTOSAR software architecture on suchmassively parallel platforms.

  • 21.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Robert Bosch GmbH, Renningen, Germany.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Arcticus Systems AB, Järfälla, Sweden.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    End-to-End Timing Analysis of Cause-Effect Chains in Automotive Embedded Systems2017In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 80, no Supplement C, p. 104-113Article in journal (Refereed)
    Abstract [en]

    Automotive embedded systems are subjected to stringent timing requirements that need to be verified. One of the most complex timing requirement in these systems is the data age constraint. This constraint is specified on cause- effect chains and restricts the maximum time for the propagation of data through the chain. Tasks in a cause-effect chain can have different activation patterns and different periods, that introduce over- and under-sampling effects, which additionally aggravate the end-to-end timing analysis of the chain. Furthermore, the level of timing information available at various development stages (from modeling of the software architecture to the software implementation) varies a lot, the complete timing information is available only at the implementation stage. This uncertainty and limited timing information can restrict the end-to-end timing analysis of these chains. In this paper, we present methods to compute end-to-end delays based on different levels of system information. The characteristics of different communication semantics are further taken into account, thereby enabling timing analysis throughout the development process of such heterogeneous software systems. The presented methods are evaluated with extensive experiments. As a proof of concept, an industrial case study demonstrates the applicability of the proposed methods following a state-of-the-practice development process.

  • 22.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Dasari, Dakshina
    Research and Technology Centre, Robert Bosch, India.
    Nelis, Vincent
    CISTER/INESC-TEC, ISEP, Portugal.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Pinho, Luis Miguel
    CISTER/INESC-TEC, ISEP, Portugal.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Investigation on AUTOSAR-Compliant Solutionsfor Many-Core Architectures2015In: Proceedings of the 18th Euromicro Conference on Digital System Design (DSD 2015), 2015Conference paper (Refereed)
    Abstract [en]

    As of today, AUTOSAR is the de facto standard inthe automotive industry, providing a common software architectureand development process for automotive applications. Whilethis standard is originally written for singlecore operated ElectronicControl Units (ECU), new guidelines and recommendationshave been added recently to provide support for multicore architectures.This update came as a response to the steady increase ofthe number and complexity of the software functions embedded inmodern vehicles, which call for the computing power of multicoreexecution environments. In this paper, we enumerate and analyzethe design options and the challenges of porting AUTOSAR-basedautomotive applications onto multicore platforms. In particular,we investigate those options when considering the emerging manycorearchitectures that provide a more scalable environment thanthe traditional multicore systems. Such platforms are suitableto enable massive parallel execution, and their design is moresuitable for partitioning and isolating the software components.

  • 23.
    Becker, Matthias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sandström, Kristian
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Many-Core based Execution Framework for IEC 61131-32015In: IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society, 2015, p. 4525-4530, article id 7392805Conference paper (Refereed)
    Abstract [en]

    Programmable logic controllers are widely used for the control of automationsystems. The standard IEC 61131-3 defines the execution model as well as theprogramming languages for such systems. Nowadays, actuators and sensorsconnect to the programmable logic controller via automation buses. While suchbuses, as well as the sensors and actuators, become more and more powerful, ashift away from the current distributed operation of automation systems, closeto the field level, becomes possible. Instead, execution of complex controlfunctions can be relocated to more powerful hardware, and technologies. Thispaper presents an execution framework for IEC 61131-3, based on a many-coreprocessors. The presented execution model exploits the characteristics of theIEC 61131-3 applications as well as the characteristics of the many-core processor,yielding a predictable execution. We present the platform architectureand an algorithm to allocate a number of IEC 61131-3 conform applications.Experimental as well as simulation based evaluation is provided.

  • 24.
    Behnam, Moris
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Inam, Rafia
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Multi-core Composability in the Face of Memory Bus Contention2012Conference paper (Refereed)
    Abstract [en]

    In this paper we describe the problem of achieving composability of independently developed real-time subsystems to be executed on a multicore platform.We evaluate existing work for achieving real-time performance on multicores and illustrate their lack with respect to composability. To better address composability we present a multi-resource server-based scheduling technique to provide predictable performance when composing multiple subsystems on a multicore platform. To achieve composability also on multicore platforms, we propose to add memory-bandwidth as an additional server resource. Tasks within our multi-resource servers are guaranteed both CPU- and memory-bandwidth; thus the performance of a server will become independent of resource usage by tasks in other servers. We are currently implementing multi-resource servers for the Enea’s OSE operating system for a P4080 8-core processor to be tested with software for a 3G-basestation.

  • 25.
    Belogiannis, Theodoros
    Mälardalen University, School of Innovation, Design and Engineering.
    Individual Stress Diagnosis from Skin Conductance sensor signals2012Independent thesis Advanced level (degree of Master (One Year)), 10 credits / 15 HE creditsStudent thesis
  • 26.
    Berg, Tobias
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Karlström, Lars
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    The construction of a Pan-Tilt unit with two digitalcameras and a PC interface2014Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
  • 27.
    Bergström, Henning
    Mälardalen University, School of Innovation, Design and Engineering.
    A Study on Timed Base Choice Criteria for Testing Embedded Software2016Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    Programs for Programmable Logic Controller (PLC) are often written in graphical or textual languages. Control engineers design and use them in systems where safety is vital, such as avionics, nuclear power plants or transportation systems. Malfunction of such a computer could have severe consequences, therefore thorough testing of PLCs are important. The Base Choice (BC) combination strategy was proposed as a suitable technique for testing software. Test cases are created based on BC strategy by varying the values of one parameter at a time while keeping the values of the other parameters fixed on the values in the base choice. However, this strategy might not be as effective when used on embedded software where parameters need to be set for a certain amount of time in order to trigger a certain interesting behavior. By incorporating time as another parameter when generating the tests, the goal is to create a better strategy that will increase not only code coverage but also fault detection compared to base choice strategy. Timed Base Choice (TBC) coverage criteria is an improvement upon the regular Base Choice criteria with the inclusion of time. We define TBC as follows: The base test case in timed base choice criteria is determined by the tester of the program. A criterion suggested by Ammann and Offutt is the “most likely value” from the point of view of the user. In addition, a time choice T is determined by the tester as the most likely time for keeping the base test case to the same values. From the base test case, new test cases are created by varying the interesting values of one parameter at a time, keeping the values of the other parameters fixed on the base test case. Each new test case is executed with the input values set for a certain amount of time determined by the time choice T. The time choice is given in time units. The research questions stated in this thesis are as follows: Research Question 1 (RQ1) How does Timed Base Choice tests compare to Base Choice tests in terms of decision coverage? Research Question 2 (RQ2) How does Timed Base Choice tests compare to Base Choice tests in terms of fault detection? In order to answer these questions, an empirical study was made in which 11 programs was tested along with respective test cases generated by BC and TBC. Each program was executed on a PLC along with the belonging test cases and several faulty programs (mutants). From this testing we got the corresponding decision coverage for each program achieved by BC and TBC respectively as well as a mutation score measuring how many of the mutated programs was detected and killed. We found that TBC outperformed BC testing both in terms of decision coverage and fault detection. Using TBC testing we managed to achieve full decision coverage on several programs that we were unable to achieve using regular BC. This shows that TBC is an improvement upon the regular BC in both ways, thus answering our previously stated research questions.

  • 28.
    Bucaioni, Alessio
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Model-driven Development Approach with Temporal Awareness for Vehicular Embedded Systems2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Considering the ubiquitousness of software in modern vehicles, its increased value and development cost, an efficient software development became of paramount importance for the vehicular domain. It has been identified that early verification of non functional properties of  vehicular embedded software such as, timing, reliability and safety, is crucial to efficiency. However, early verification of non functional properties is hard to achieve with traditional software development approaches due to the abstraction and the lack of automation of these methodologies.

     

    This doctoral thesis aims at improving efficiency in vehicular embedded software development by minimising the need for late, expensive and time consuming software modifications with early design changes, identified through timing verification, which usually are cheaper and faster. To this end, we introduce a novel model-driven approach which exploits the interplay of two automotive-specific modelling languages for the representation of functional and execution models and defines a suite of model transformations for their automatic integration.

     

    Starting from a functional model (expressed by means of EAST-ADL), all the execution models (expressed by means of the Rubus Component Model) entailing unique timing configurations are derived. Schedulability analysis selects the set of the feasible execution models with respect to specified timing requirements. Eventually, a reference to the selected execution models along with their analysis results is automatically created in the related functional model to allow the engineer to investigate them.

     

    The main scientific contributions of this doctoral thesis are i) a metamodel definition for the Rubus Component Model, ii) an automatic mechanism for the generation of Rubus models from EAST-ADL, iii) an automatic mechanism for the selection and back-propagation of the analysis results and related Rubus models to design level and iv) a compact notation for visualising the selected Rubus models by means of a single execution model.

  • 29.
    Bucaioni, Alessio
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Arcticus Systems AB, Jarfalla, Sweden.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Arcticus Systems AB, Jarfalla, Sweden.
    Cicchetti, Antonio
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sjödin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Exploring Timing Model Extractions at EAST-ADL Design-level Using Model Transformations2015In: Proceedings - 12th International Conference on Information Technology: New Generations, ITNG 2015, 2015, Vol. Article number 7113538, p. 596-600Conference paper (Refereed)
    Abstract [en]

    We discuss the problem of extracting control and data flows from vehicular distributed embedded systems at higher abstraction levels during their development. Unambiguous extraction of control and data flows is vital part of the end-to-end timing model which is used as input by the end-to end timinganalysis engines. The goal is to support end-to-end timing analysis at higher abstraction levels. In order to address the problem, we propose a two-phase methodology that exploits the principles of ModelDriven Engineering and Component Based Software Engineering. Using this methodology, the software architecture at a higher level is automatically transformed to all legal implementation-level models. The end-to-end timing analysis is performed on each generated implementation-level model and the analysis results are fed back to the design-level model. This activity supports design space exploration, modelrefinement and/or remodeling at higher abstraction levels for tuning the timing behavior of the system.

  • 30.
    Cai, Simin
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Gallina, Barbara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nyström, Dag
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Seceleanu, Cristina
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Towards the verification of temporal data consistency in Real-Time Data Management2016In: 2016 2nd International Workshop on Modelling, Analysis, and Control of Complex CPS, CPS Data 2016, 2016, article id Article number 7496422Conference paper (Refereed)
    Abstract [en]

    Many Cyber-Physical Systems (CPSs) require both timeliness of computation and temporal consistency of their data. Therefore, when using real-time databases in a real-time CPS application, the Real-Time Database Management Systems (RTDBMSs) must ensure both transaction timeliness and temporal data consistency. RTDBMSs prevent unwanted interferences of concurrent transactions via concurrency control, which in turn has a significant impact on the timeliness and temporal consistency of data. Therefore it is important to verify, already at early design stages that these properties are not breached by the concurrency control. However, most often such early on guarantees of properties under concurrency control are missing. In this paper we show how to verify transaction timeliness and temporal data consistency using model checking. We model the transaction work units, the data and the concurrency control mechanism as a network of timed automata, and specify the properties in TCTL. The properties are then checked exhaustively and automatically using the UPPAAL model checker. 

  • 31.
    Campeanu, Gabriel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    GPU Support for Component-based Development of Embedded Systems2018Doctoral thesis, monograph (Other academic)
    Abstract [en]

    One pressing challenge of many modern embedded systems is to successfully deal with the considerable amount of data that originates from the interaction with the environment. A recent solution comes from the use of GPUs. Equipped with a parallel execution model, the GPU excels in parallel processing applications, providing an improved performance compared to the CPU.

    Another trend in the embedded systems domain is the use of component-based development. This software engineering paradigm that promotes construction of applications through the composition of software components, has been successfully used in the development of embedded systems. However, the existing approaches provide no specific support to develop embedded systems with GPUs. As a result, components with GPU capability need to encapsulate all the required GPU information in order to be successfully executed by the GPU. This leads to component specialization to specific platforms, hence drastically impeding component reusability.

    Our main goal is to facilitate component-based development of embedded systems with GPUs. We introduce the concept of flexible component which increases the flexibility to design embedded systems with GPUs, by allowing the system developer to decided where to place the component, i.e., either on the CPU or GPU. Furthermore, we provide means to automatically generate the required information for flexible components corresponding to their hardware placement, and to improve component communication. Through the introduced support, components with GPU capability are platform-independent, being capable to be executed on a large variety of hardware (i.e., platforms with different GPU characteristics). Furthermore, an optimization step is introduced, which groups connected flexible components into single entities that behave as regular components. Dealing with components that can be executed either by the CPU or GPU, we also introduce an allocation optimization method. The proposed solution, implemented using a mathematical solver, offers alternative options in optimizing particular system goals (e.g., memory and energy usage).

  • 32.
    Campeanu, Gabriel
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Mubeen, Saad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. IS (Embedded Systems).
    Improving Run-Time Memory Utilization of Component-based Embedded Systems with Non-Critical Functionality2017In: The Twelfth International Conference on Software Engineering Advances ICSEA 2017, 2017Conference paper (Refereed)
    Abstract [en]

    Many contemporary embedded systems have to deal with huge amount of data, coming from the interaction with the environment, due to their data-intensive applications. However, due to some inherent properties of these systems, such as limited energy and resources (compute and storage), it is important that the resources should be used in an efficient way. For example, camera sensors of a robot may provide low-resolution frames for positioning itself in an open environment, and high-resolution frames to analyze detected objects. Component-based software development techniques and models have proven to be efficient for the development of these systems. Many component models used in the industry (e.g., Rubus, IEC 61131) allocate, at the system initialization, enough resources to satisfy the demands of the system's critical functionality. These resources are retained by the critical functionality even when they are not fully utilized. In this paper, we introduce a method that, when possible, distributes the unused memory of the critical functionality to the non-critical functionality in order to improve its performance. The method uses a monitoring solution that checks the memory utilization, and triggers the memory distribution whenever possible. As a proof of concept, we realize the proposed method in an industrial component model. As an evaluation, we use an underwater robot case study to evaluate the feasibility of the proposed solution.

  • 33.
    Campeanu, Gabriel
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Saadatmand, Mehrdad
    SICS Swedish ICT, Västerås, Sweden.
    A 2-layer component-based architecture for heterogeneous CPU-GPU embedded systems2016In: Advances in Intelligent Systems and Computing, Volume 448, 2016, p. 629-639Conference paper (Refereed)
    Abstract [en]

    Traditional embedded systems are evolving into heterogeneous systems in order to address new and more demanding software requirements. Modern embedded systems are constructed by combining different computation units, such as traditional CPUs with Graphics Processing Units (GPUs). Adding GPUs to conventional CPU-based embedded systems enhances the computation power but also increases the complexity in developing software applications. A method that can help to tackle and address the software complexity issue of heterogeneous systems is component-based development. The allocation of the software application onto the appropriate computation node is greatly influenced by the system information load. The allocation process is increased in difficulty when we use, instead of common CPU-based systems, complex CPU-GPU systems. This paper presents a 2-layer component-based architecture for heterogeneous embedded systems, which has the purpose to ease the software-to-hardware allocation process. The solution abstracts the CPU-GPU detailed component-based design into single software components in order to decrease the amount of information delivered to the allocator. The last part of the paper describes the activities of the allocation process while using our proposed solution, when applied on a real system demonstrator.

  • 34.
    Castellanos Ardila, Julieth Patricia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Gallina, Barbara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    UL Muram, Faiz
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Transforming SPEM 2.0-compatible process models into models checkable for compliance2018In: Communications in Computer and Information Science, Springer Verlag , 2018, Vol. 918, p. 233-247Conference paper (Refereed)
    Abstract [en]

    Manual compliance with process-based standards is time-consuming and prone-to-error. No ready-to-use solution is currently available for increasing efficiency and confidence. In our previous work, we have presented our automated compliance checking vision to support the process engineer’s work. This vision includes the creation of a process model, given by using a SPEM 2.0 (Systems & Software Process Engineering Metamodel)-reference implementation, to be checked by Regorous, a compliance checker used in the business context. In this paper, we move a step further for the concretization of our vision by defining the transformation, necessary to automatically generate the models required by Regorous. Then, we apply our transformation to a small portion of the design phase recommended in the rail sector. Finally, we discuss our findings, and present conclusions and future work. 

  • 35.
    Chandran, Kumar
    Vikram Sarabhai Bhavan, Anushaktinagar, Bombay, India .
    STANDBY REDUNDANCY AT SYSTEM AND COMPONENT LEVELS--A COMPARISON1995In: Microelectronics and Reliability, ISSN 0026-2714, Vol. 35, no 4, p. 751-752Article in journal (Refereed)
    Abstract [en]

    This note compares the lifetime of a series and a parallel system when standby redundancy is provided at system and component level. The system lifetime is longer when standby redundancy is added at the component level for a series system whereas in the parallel system, standby redundancy at the system level is more efficient.

  • 36.
    Charbachi, Peter
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Eklund, Linus
    Mälardalen University, School of Innovation, Design and Engineering.
    Thesis for the Degree of Bachelor of Science in Computer Science by Peter Charbachi and Linus Eklund: PAIRWISE TESTING FOR PLC EMBEDDED SOFTWARE2016Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    In this thesis we investigate the use of pairwise testing for PLC embedded software. We compare these automatically generated tests with tests created manually by industrial engineers. The tests were evaluated in terms of fault detection, code coverage and cost. In addition, we compared pairwise testing with randomly generated tests of the same size as pairwise tests. In order to automatically create test suites for PLC software a previously created tool called Combinatorial Test Tool (CTT) was extended to support pairwise testing using the IPOG algorithm. Once test suites were created using CTT they were executed on real industrial programs. The fault detection was measured using mutation analysis. The results of this thesis showed that manual tests achieved better fault detection (8% better mutation score in average) than tests generated using pairwise testing. Even if pairwise testing performed worse in terms of fault detection than manual testing, it achieved better fault detection in average than random tests of the same size. In addition, manual tests achieved in average 97.29% code coverage compared to 93.95% for pairwise testing, and 84.79% for random testing. By looking closely on all tests, manual testing performed equally good as pairwise in terms of achieved code coverage. Finally, the number of tests for manual testing was lower (12.98 tests in average) compared to pairwise and random testing (21.20 test in average). Interestingly enough, for the majority of the programs pairwise testing resulted in fewer tests than manual testing.

  • 37.
    Charbachi, Peter
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ferrario, Filippo
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Methods for Automatic Hydraulics Calibration in Construction Equipment2018Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In this thesis we investigate the problem of automatic calibration and control of hydraulic components in the domain of construction equipment. Methods that are able to remove a costly manual approach in favour of an automatic one are investigated and evaluated. The thesis aims to investigate what methods are available in achieving this goal as well as evaluate the performance and applicability of such methods in the domain of construction equipment. The literature indicates that a great focus is put on learning a model of the plant at run time in order to provide accurate control. Common approaches to the problem are the Recursive Least Square method and PID controllers for non-linear systems, but other methods are also present, such as the Nodal Link Perceptron Network (NLPN). The methods chosen to be compared are the existing method of manually calibrating two set points for start and end current and interpolating between them; the use of a PI controller with a static line inverse model; a PI controller with a static curve inverse model; a PI controller with an NLPN adaptive inverse model and lastly, a completely NLPN based control strategy. The methods were implemented in Matlab Simulink and evaluated in simulations based on data collected from real wheel loaders in the construction equipment domain, produced by Volvo CE. The simulations are performed on data from three machines and were evaluated twice for the adaptive methods in order to evaluate how well the methods improved. The results were then evaluated in terms of average absolute error, as well as a discussion of the behaviour shown in the plots. The evaluations indicate that the most effective method for control is the PI controller using a static line inverse model. The method produces the smallest average error of both actions evaluated, lifting and lowering of the boom, while the complete NLPN solution provide the worst results.

  • 38.
    Chiru, Cezar
    Mälardalen University, School of Innovation, Design and Engineering.
    Resource based analysis of Ethernet communication between software partitions2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Nowadays, Industrial Control Systems (ICSs) are becoming larger and implement more complex functions. Therefore, technologies that are currently used to implement these functions, like hardware platforms and communication protocols might soon become unusable due to the lack of resources. The industry is trying to adopt new technologies that will allow these functionalities to be developed without an increase in the size of the equipment, or of the development costs. To enumerate some of these technologies: virtualization, multi-core technologies are the ones that show the biggest potential. Because these technologies are not mature, research has to be done in order to fully maximize their potential. Another technology that is highly used by the industry is the Ethernet communication protocol. It presents some advantages, but due to the non-real-time nature of the applications that it was designed for, it has to be extended in order to be used in real-time applications. The objective of this thesis work is to model an Ethernet network comprised of software partitions so that it can provide timing guarantees for the traffic that traverses the network. A Response Time Analysis for real-time flows over such networks is proposed. The model and the RTA are evaluated by experiments.

  • 39.
    Ciccozzi, Federico
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Corcoran, Diarmuid
    Ericsson AB, Kista, Sweden.
    Seceleanu, Tiberiu
    ABB Corporate Research, Vasteras, Sweden.
    Scholle, Detlef
    Alten Sverige AB, Sweden.
    SMARTCore: Boosting Model-Driven Engineering of Embedded Systems for Multicore2015In: Proceedings - 12th International Conference on Information Technology: New Generations, ITNG 2015, 2015, Vol. Article number 7113454, p. 89-94Conference paper (Refereed)
    Abstract [en]

    Thanks to continuous advances in both software and hardware technologies the power of modern embedded systems is ever increasing along with their complexity. Among the others, Model-Driven Engineering has grown consideration for mitigating this complexity through its ability to shift the focus of the development from hand-written code to models from which correct-by-construction implementation is automatically generated. However, the path towards correctness-by-construction is often twisted by the inability of current MDE approaches to preserve certain extra-functional properties such as CPU and memory usage, execution time and power consumption. With SMARTCore we address open challenges, described in this paper together with an overview of possible solutions, in modelling, generating code from models, and exploiting back-propagated extra-functional properties observed at runtime for deployment optimisation of embedded systems on multicore. SMARTCore brings together world leading competence in software engineering, model-driven engineering for embedded systems (Mälardalen University), and market leading expertise in the development of these systems in different business areas (ABB Corporate Research, Ericsson AB, Alten Sweden AB).

  • 40.
    Crnkovic, Ivica
    Mälardalen University, Department of Computer Science and Electronics.
    Component-based Software Engineering for Embedded Systems2005In: From MDD Concepts to Experiments and Illustrations, John Wiley & Sons, 2005, p. 712-713Chapter in book (Other academic)
    Abstract [en]

    Component-based development (CBD) is established as a standard approach in many domains. The most attractive parts of CBD come from its business side: increasing reuse and development efficiency. On other side many technical aspects are still remaining as challenges. This is in particular true in domains of embedded and dependable systems. The seminar will give the basic characteristics of component-based software development, then challenges and current practice and research directions.

  • 41.
    Dardar, Raghad
    Mälardalen University, School of Innovation, Design and Engineering.
    Building a Safety Case in Compliance with ISO 26262 for Fuel LevelEstimation and Display System2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Nowadays, road vehicles, including trucks, are characterized by an increasedcomplexity due to a greater variety of software, and a greater number of sensorsand actuators. As a consequence, there is an increased risk in termsof software or hardware failures that could lead to unacceptable hazards.Thus safety, more precisely functional safety, is a crucial property that mustbe ensured to avoid or mitigate these potential unacceptable hazards. Inthe automotive domain, recently (November 2011), the ISO-26262 safetystandard has been introduced to provide appropriate requirements and processes.More specically, the standard denes the system development processthat must be carried out to achieve a system that can be consideredacceptably safe. To be released on the market, systems must be certied,proofs that the systems are acceptably safe must be provided in terms of astructured argument, known as safety case, which inter-relates evidence andclaims. Certication authorities are in charge of evaluating the validity ofsuch safety cases. In the automotive domain, certication and compliancewith the standard ISO-26262 is becoming mandatory. By now, trucks donot have to be compliant with the standard. However, it is likely that by2016 they will have to. Scania is one of the leading companies in trucksdevelopment. To be ready by 2016, Scania is interested in investigatingISO-26262 as well as safety case provision. Thus this thesis focuses on theprovision of a safety case in the context of ISO-26262 for Fuel Level Estimationand Display System (FLEDS), which is one of the safety-criticalsystems in Scania.1

  • 42.
    de Berardinis, J.
    et al.
    The University of Manchester, School of Computer Science, United Kingdom.
    Forcina, Giorgio
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Jafari, A.
    Reykjavik University, School of Computer Science, Reykjavik, Iceland.
    Sirjani, Marjan
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. University, School of Computer Science, Reykjavik, Iceland.
    Actor-based macroscopic modeling and simulation for smart urban planning2018In: Science of Computer Programming, ISSN 0167-6423, E-ISSN 1872-7964, Vol. 168, p. 142-164Article in journal (Refereed)
    Abstract [en]

    Assessing the impacts of a mobility initiative prior to deployment is a complex task for both urban planners and transport companies. Computational models like Tangramob offer an agent-based framework for simulating the evolution of urban traffic after the introduction of new mobility services. However, simulations can be computationally expensive to perform due to their iterative nature and the microscopic representation of traffic. To address this issue, we designed a simplified model architecture of Tangramob in Timed Rebeca (TRebeca) and we developed a tool-chain for the generation runnable instances of this model starting from the same input files of Tangramob. Running TRebeca models allows users to get an idea of how the mobility initiatives under study affect the traveling experience of commuters, in a short time and without the need to use the simulator during this first experimental step. Then, once a subset of these initiatives is identified according to user's criteria, it is reasonable to simulate them with Tangramob in order to get more detailed results. To validate this approach, we compared the output of both the simulator and the TRebeca model on a collection of mobility initiatives. The correlation between the results demonstrates the usefulness of using TRebeca models for unconventional contexts of application.

  • 43.
    Dersten, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Axelsson, Jakob
    Mälardalen University, School of Innovation, Design and Engineering.
    Fröberg, Joakim
    Mälardalen University, School of Innovation, Design and Engineering.
    An empirical study of refactoring decisions in embedded software and systems2012In: Procedia Computer Science, ISSN 1877-0509, E-ISSN 1877-0509, Vol. 8, p. 279-284Article in journal (Refereed)
    Abstract [en]

    This paper describes an empirical study of decision-making when changing the architecture in embedded systems. A refactoring of the system architecture often gives effects on both system properties and functions in the company organization, and there is a lack of efficient analysis methods for decision support in the system architecture process. This study investigates the information needed to make a decision about a system refactoring. Scenario-based interviews have been conducted with managers and system architects from companies developing embedded systems. The results show that the companies investigate similar issues regardless of their industry sector. The most wanted information prior to a decision is also presented.

  • 44.
    Dersten, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Axelsson, Jakob
    Mälardalen University, School of Innovation, Design and Engineering.
    Fröberg, Joakim
    Mälardalen University, School of Innovation, Design and Engineering.
    Characteristics of a System Refactoring Process in Embedded Systems Development2012Conference paper (Refereed)
  • 45.
    Didic, Alma
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nikolaidis, Pavlos
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Real-time control in industrial IoT2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Great advances in cloud computing have drawn the interest of industry. Cloud infrastructures areused, mainly, for monitoring the shop oor. In recent years cloud technologies combined with IoTtechnologies have initiated the eort to close loops between industrial applications and cloud infras-tructures. This thesis examines the eect of including remote servers, both local and centralized,in the closed control loop. Specically, we investigate how delays and jitter aect the closed controlloop. A prototype is developed to include servers on a control loop and inject delays and jitter inthe network. Furthermore, delay mitigation mechanisms are proposed and, using the prototype, anumber of experiments are performed to evaluate them. The mitigation mechanisms focus mainlyon delays and jitter that are larger than the period of closed control loop. The proposed mechanismsimprove the closed control loop response but still fall short compared to the performance of the closecontrol loop when it executes locally, without any servers included. We also, show that local serverscan be included in the closed control loop without signicant degradation in the performance of thesystem.

  • 46.
    Du, Yong
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Online Admission Control for Multi-Switch Ethernet Networks2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The trend of using switched Ethernet protocols in real-time domains, where timing requirements exist, is increasing. This is mainly because of the features of switched Ethernet, such as its high throughput and availability. Compared to other network technologies, switched Ethernet can support higher data rate. Besides the timing requirements, that must be fulfilled in real-time applications, another requirement is normally demanded in real-time systems. This requirement is the ability of changing, adding or removing the messages crossing the network during run-time. This ability is known as on-line reconfiguration, and it should be done in a way that the real-time behavior of the network is not violated. This means that, the guarantee of meeting the timing requirements for the messages should not be affected by the changes in the network. In this thesis, we focus on on-line reconfiguration for multi-hop HaRTES architecture, which is a real-time switched Ethernet network. The HaRTES switch is a modified Ethernet switch that provides real-time guarantees as well as an admission control to be used for on-line reconfiguration. We study the existing reconfiguration methods including centralized and distributed approaches. Then, we propose a solution to provide on-line reconfiguration for the multi-hop HaRTES architecture, based on the studied methods. For this purpose, we use a hybrid method to achieve the advantages of both traditional centralized and distributed approaches. Moreover, we perform two different experiments. In the first experiment we focus on the decision making part of the method. The decision making part decides whether the requested reconfiguration is feasible. We calculate the time required to make the decision in different network settings. In the second experiment, we focus on the entire reconfiguration process, where the decision making is part of it. Again, we show the time needed to do the reconfiguration in several network settings. Finally, we conclude the thesis by presenting possible future works

  • 47.
    Duff, Gerard
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    App enabling environment for Volvo CE platforms2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
  • 48.
    Duff, Gerard
    Mälardalen University, School of Innovation, Design and Engineering.
    App enabling environment to Volvo CE platforms2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis was submitted to the faculty of Innovation, Design and Technology, IDT, at Mälardalen university in Västerås, Sweden as a partial fulfillment of the requirements to obtain the M.Sc. in computer science, specializing in embedded systems. The work presented was carried out in the months January to June in 2014 partially in Volvo Construction Equipment, Volvo CE, Eskilstuna, and partially at Mälardalen university in Västerås.

    Federated Resilient Embedded Systems Technology for AUTOSAR, FRESTA, is a collaborative project between Volvo and the Swedish Institute of Computer Science, SICS, that aims to make it possible to add third party applications to vehicle’s computer systems without compromising system security and robustness. The mechanism is developed by SICS for AUTOSAR, AUTomotive Open System ARchitecture, an open standardized automotive software architecture for vehicles.

    The following report documents the efforts to study and port the FRESTA mechanism to the Volvo CE platform, and develop a Java application to test the porting. The investigation will aspire to determine if it is feasible to introduce Java based third party applications to resource constrained embedded systems, without causing a deterioration in the predictability and security of the system.

  • 49.
    Ekstrand, Fredrik
    Mälardalen University, School of Innovation, Design and Engineering.
    Resource Optimized Stereo Matching in Reconfigurable Hardware for Autonomous Systems2011Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    There is a need for compact, high-speed, and low-power vision systems for enabling real-time mobile autonomous applications. The best approach to achieve this is to implement the bulk of the application in hardware. Reconfigurable hardware meet these requirements without the limitation of fixed functionality that accompanies application-specific circuits. Resource constraints of reconfigurable hardware calls for optimized implementations i terms of resource usage with maintained performance.

    The research group in Robotics at Mälardalen University is moving toward the completion of a reconfigurable hardware-platform for stereo vision, coupled with a compact embedded computer. This system will incorporate hardware-based preprocessing components enabling visual perception for autonomous machines. This thesis covers the reconfigurable hardware section of the vision system concerning the realization of scene depth extraction. It shows the advantages of image preprocessing in hardware and propose a resource optimized approach to stereo matching. The work quantifies the impact of reduced resource utilization and a desire for increased accuracy in disparity estimation. The implemented stereo matching approach performs on par with recent similar implementations in terms of accuracy, but excels in terms of resource utilization and resource sharing, as the external memory requirement is removed for larger images.

    Future work aims to further include processes for navigation, and structure and object recognition. Furthermore, the system will be adapted to real world scenarios, both indoors and outdoors.

  • 50.
    Ekstrand, Fredrik
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Ahlberg, Carl
    Mälardalen University, School of Innovation, Design and Engineering.
    Ekström, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Asplund, Lars
    Mälardalen University, School of Innovation, Design and Engineering.
    Spampinato, Giacomo
    Mälardalen University, School of Innovation, Design and Engineering.
    Resource Limited Hardware-based Stereo Matching for High-Speed Vision System2011In: ICARA 2011 - Proceedings of the 5th International Conference on Automation, Robotics and Applications, 2011, p. 465-469Conference paper (Refereed)
    Abstract [en]

    This paper proposes a limited implementation of areabasedstereo matching for minimal resource utilization. It shows that it is possible to achieve an acceptable disparity map without the use of expensive resources. The matching accuracy for the single-row SAD can even outperform that of its full-row counterpart. Additionally, it excels in terms of frame rate and resource utilization, and is highly suitable for real-time stereo-vision systems.

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