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  • 1.
    Abrahamsson, Henrik
    Mälardalen University, School of Innovation, Design and Engineering.
    Internet Traffic Management2008Licentiate thesis, comprehensive summary (Other scientific)
  • 2.
    Abrahamsson, Henrik
    Mälardalen University, School of Innovation, Design and Engineering.
    Network overload avoidance by traffic engineering and content caching2012Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The Internet traffic volume continues to grow at a great rate, now driven by video and TV distribution. For network operators it is important to avoid congestion in the network, and to meet service level agreements with their customers.  This thesis presents work on two methods operators can use to reduce links loads in their networks: traffic engineering and content caching.

    This thesis studies access patterns for TV and video and the potential for caching.  The investigation is done both using simulation and by analysis of logs from a large TV-on-Demand system over four months.

    The results show that there is a small set of programs that account for a large fraction of the requests and that a comparatively small local cache can be used to significantly reduce the peak link loads during prime time. The investigation also demonstrates how the popularity of programs changes over time and shows that the access pattern in a TV-on-Demand system very much depends on the content type.

    For traffic engineering the objective is to avoid congestion in the network and to make better use of available resources by adapting the routing to the current traffic situation. The main challenge for traffic engineering in IP networks is to cope with the dynamics of Internet traffic demands.

    This thesis proposes L-balanced routings that route the traffic on the shortest paths possible but make sure that no link is utilised to more than a given level L. L-balanced routing gives efficient routing of traffic and controlled spare capacity to handle unpredictable changes in traffic.  We present an L-balanced routing algorithm and a heuristic search method for finding L-balanced weight settings for the legacy routing protocols OSPF and IS-IS. We show that the search and the resulting weight settings work well in real network scenarios.

  • 3.
    Abrahamsson, Henrik
    et al.
    Swedish Institute of Computer Science, Kista, Sweden.
    Björkman, Mats
    Mälardalen University, School of Innovation, Design and Engineering.
    Caching for IPTV distribution with time-shift2013In: 2013 International Conference on Computing, Networking and Communications, ICNC 2013, IEEE , 2013, p. 916-921Conference paper (Refereed)
    Abstract [en]

    Today video and TV distribution dominate Internet traffic and the increasing demand for high-bandwidth multimedia services puts pressure on Internet service providers. In this paper we simulate TV distribution with time-shift and investigate the effect of introducing a local cache close to the viewers. We study what impact TV program popularity, program set size, cache replacement policy and other factors have on the caching efficiency. The simulation results show that introducing a local cache close to the viewers significantly reduces the network load from TV-on-Demand services. By caching 4% of the program volume we can decrease the peak load during prime time by almost 50%. We also show that the TV program type and how program popularity changes over time can have a big influence on cache hit ratios and the resulting link loads

  • 4.
    Abrahamsson, Henrik
    et al.
    Swedish Institute of Computer Science.
    Björkman, Mats
    Mälardalen University, School of Innovation, Design and Engineering.
    Simulation of IPTV caching strategies2010In: Proceedings of the 2010 International Symposium on Performance Evaluation of Computer and Telecommunication Systems, 2010, p. 187-193Conference paper (Refereed)
    Abstract [en]

    IPTV, where television is distributed over the Internet Protocol in a single operator network, has become popular and widespread. Many telecom and broadband companies have become TV providers and distribute TV channels using multicast over their backbone networks. IPTV also means an evolution to time-shifted television where viewers now often can choose to watch the programs at any time. However, distributing individual TV streams to each viewer requires a lot of bandwidth and is a big challenge for TV operators. In this paper we present an empirical IPTV workload model, simulate IPTV distribution with time-shift, and show that local caching can limit the bandwidth requirements significantly.

  • 5.
    Abrahamsson, Henrik
    et al.
    Swedish Institute of Computer Science, Kista, Sweden.
    Nordmark, Mattias
    TeliaSonera AB, Stockholm, Sweden .
    Program popularity and viewer behaviour in a large TV-on-Demand system2012In: IMC '12 Proceedings of the 2012 ACM conference on Internet measurement conference, New York: ACM , 2012, p. 199-210Conference paper (Refereed)
    Abstract [en]

    Today increasingly large volumes of TV and video are distributed over IP-networks and over the Internet. It is therefore essential for traffic and cache management to understand TV program popularity and access patterns in real networks.

    In this paper we study access patterns in a large TV-on-Demand system over four months. We study user behaviour and program popularity and its impact on caching. The demand varies a lot in daily and weekly cycles. There are large peaks in demand, especially on Friday and Saturday evenings, that need to be handled.

    We see that the cacheability, the share of requests that are not first-time requests, is very high. Furthermore, there is a small set of programs that account for a large fraction of the requests. We also find that the share of requests for the top most popular programs grows during prime time, and the change rate among them decreases. This is important for caching. The cache hit ratio increases during prime time when the demand is the highest, and aching makes the biggest difference when it matters most.

    We also study the popularity (in terms of number of requests and rank) of individual programs and how that changes over time. Also, we see that the type of programs offered determines what the access pattern will look like.

  • 6.
    Afshar, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Bril, Reinder J.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Technische Universiteit Eindhoven, Eindhoven, Netherlands.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Resource Sharing Under Global Scheduling with Partial Processor Bandwidth2015In: 2015 10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015 - Proceedings, 2015, p. 195-206Conference paper (Refereed)
    Abstract [en]

    Resource efficient approaches are of great importance for resource constrained embedded systems. In this paper, we present an approach targeting systems where tasks of a critical application are partitioned on a multi-core platform and by using resource reservation techniques, the remaining bandwidth capacity on each core is utilized for one or a set of non-critical application(s). To provide a resource efficient solution and to exploit the potential parallelism of the extra applications on the multi-core processor, global scheduling is used to schedule the tasks of the non-critical applications. Recently a specific instantiation of such a system has been studied where tasks do not share resources other than the processor. In this paper, we enable semaphore-based resource sharing among tasks within critical and non-critical applications using a suspension-based synchronization protocol. Tasks of non-critical applications have partial access to the processor bandwidth. The paper provides the systems schedulability analysis where blocking due to resource sharing is bounded. Further, we perform experimental evaluations under balanced and unbalanced allocation of tasks of a critical application to cores.

  • 7.
    Asplund, Lars
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Johnson, B.
    Mälardalen University, School of Innovation, Design and Engineering.
    Lundqvist, Kristina
    Mälardalen University, School of Innovation, Design and Engineering.
    Burns, Alan
    Session Summary: The Ravenscar Profile and Implementation Issues1999In: ACM SIGAda Ada Letters, Vol. XIX, no 2, p. 12-14Article in journal (Other academic)
  • 8.
    Avritzer, A
    et al.
    Siemens Corporate Research, USA.
    Tanikella, R
    Siemens Corporate Research, USA.
    James, K
    Siemens Corporate Research, USA.
    Cole, R
    JHU, Applied Physics Laboratory, USA.
    weyuker, elaine
    AT and T Labs, USA.
    Monitoring for Security Intrusion using Performance Signatures2010In: WOSP/SIPEW'10 - Proceedings of the 1st Joint WOSP/SIPEW International Conference on Performance Engineering, 2010, p. 93-103Conference paper (Refereed)
    Abstract [en]

    A new approach for detecting security attacks on software systems by monitoring the software system performance signatures is introduced. We present a proposed architecture for security intrusion detection using off-the-shelf security monitoring tools and performance signatures. Our approach relies on the assumption that the performance signature of the well-behaved system can be measured and that the performancesignature of several types of attacks can be identified. This assumption has been validated for operations support systems that are used to monitor large infrastructures and receive aggregated traffic that is periodic in nature. Examples of such infrastructures include telecommunications systems, transportation systems and power generation systems. In addition, significant deviation from well-behaved system performance signatures can be used to trigger alerts about new types of security attacks. We used a custom performance benchmark and five types of security attacks to deriveperformance signatures for the normal mode of operation and the security attack mode of operation. We observed that one of the types of thesecurity attacks went undetected by the off-the-shelf security monitoring tools but was detected by our approach of monitoring performance signatures. We conclude that an architecture for security intrusion detection can be effectively complemented by monitoring of performance signatures.

  • 9.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering.
    Hierarchical Real Time Scheduling and Synchronization2008Licentiate thesis, comprehensive summary (Other scientific)
    Abstract [en]

     

    The Hierarchical Scheduling Framework (HSF) has been introduced to enable compositional schedulability analysis and execution of embedded software systems with real-time constraints. In this thesis, we consider a system consisting of a number of semi-independent components called subsystems, and these subsystems are allowed to share logical resources. The HSF provides CPU-time to the subsystems and it guarantees that the individual subsystems respect their allocated CPU budgets. However, if subsystems are allowed to share logical resources, extra complexity with respect to analysis and run-time mechanisms is introduced. In this thesis we address three issues related to hierarchical scheduling of semi-independent subsystems. In the first part, we investigate the feasibility of implementing the hierarchical scheduling framework in a commercial operating system, and we present the detailed figures of various key properties with respect to the overhead of the implementation.

    In the second part, we studied the problem of supporting shared resources in a hierarchical scheduling framework and we propose two different solutions to support resource sharing. The first proposed solution is called SIRAP, a synchronization protocol for resource sharing in hierarchically scheduled open real-time systems, and the second solution is an enhanced overrun mechanism.

    In the third part, we present a resource efficient approach to minimize system load (i.e., the collective CPU requirements to guarantee the schedulability of hierarchically scheduled subsystems). Our work is motivated from a tradeoff between reducing resource locking times and reducing system load. We formulate an optimization problem that determines the resource locking times of each individual subsystem with the goal of minimizing the system load subject to system schedulability. We present linear complexity algorithms to find an optimal solution to the problem, and we prove their correctness

     

     

     

     

     

     

     

  • 10.
    Behnam, Moris
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Shin, Insik
    Åsberg, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Bril, Reinder
    Technische Universiteit Eindhoven.
    Towards Hierarchical Scheduling in VxWorks2008In: OSPERT 2008, Proceedings of the Fourth International Workshop on Operating Systems Platforms for Embedded Real-Time Applications, 2008, p. 63-72Conference paper (Refereed)
    Abstract [en]

    Over the years, we have worked on hierarchical schedulingframeworks from a theoretical point of view. In thispaper we present our initial results of the implementationof our hierarchical scheduling framework in a commercialoperating system VxWorks. The purpose of the implementationis twofold: (1) we would like to demonstrate feasibilityof its implementation in a commercial operating system,without having to modify the kernel source code, and (2) wewould like to present detailed figures of various key propertieswith respect to the overhead of the implementation.During the implementation of the hierarchical scheduler,we have also developed a number of simple task schedulers.We present details of the implementation of Rate-Monotonic(RM) and Earliest Deadline First (EDF) schedulers. Finally,we present the design of our hierarchical schedulingframework, and we discuss our current status in the project.

  • 11.
    Behnam, Moris
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Shin, Insik
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering.
    Nolin, Mikael
    Mälardalen University, School of Innovation, Design and Engineering.
    Scheduling of Semi-Independent Real-Time Components: Overrun Methods and Resource Holding Times2008In: Proceedings of the 13th IEEE International Conference on Emerging echnologies and Factory Automation (ETFA’08), 2008, p. 575-582Conference paper (Refereed)
    Abstract [en]

    The Hierarchical Scheduling Framework (HSF) has been introduced as a design-time framework enabling compositional schedulability analysis of embedded software systems with real-time properties. In this paper a system consists of a number of semi-independent components called subsystems. Subsystems are developed independently and later integrated to form a system. To support this design process, our proposed methods allow nonintrusive configuration and tuning of subsystem timing behaviour via subsystem interfaces for selecting scheduling parameters. This paper considers two methods to handle overruns due to resource sharing between subsystems in the HSF. We present the scheduling algorithms for overruns and their associated schedulability analysis, together with analysis that shows under what circumstances one or the other overrun method is preferred. Furthermore, we show how to calculate resource-holding times within our framework.

  • 12.
    Björnhager, Jens
    Mälardalen University, School of Innovation, Design and Engineering.
    CRL2ALF: En översättare från PowerPC till ALF2011Independent thesis Advanced level (degree of Master (One Year)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Real-time systems put tough timing requirements on the software running on them. The programs must behave deterministically and respond within set time limits. With these demands comes a higher demand on verification tools. The goal of a WCET (Worst Case Execution Time) analysis is to derive the upper bound of a program's execution time. SWEET (SWEdish Execution Time) is a tool for WCET analysis developed by a research group at Mälardalen University.

    PowerPC is a classic processor architecture that was developed by Apple, Motorola and IBM and was released in 1991. It has been used in older versions of Apple's Macintosh computers and in video game consoles such as the GameCube from Nintendo, and is a popular choice for embedded solutions.

    Previously you could only do analyses on code generated from C in SWEET. The goal of this MSC thesis was to construct a converter from PowerPC binaries to the program format that SWEET uses for its analyses, ALF, with the help of the third-party tool aiT from AbsInt GmbH.

    The result is a - with the exception of floating-point instructions - complete converter from PowerPC programs to ALF. Most of the generated program files have been tested within SWEET with successful results. 

  • 13.
    Daneryd, Oscar
    Mälardalen University, School of Innovation, Design and Engineering.
    Congestion Management at the Network Edge2014Independent thesis Basic level (university diploma), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    In the Internet of today there is a demand for both high bandwidth and low delays. Bandwidth-heavy applications such as large downloads or video streaming compete with more delay-sensitive applications; web-browsing, VoIP and video games. These applications represent a growing share of Internet traffic.

    Buffers are an essential part of network equipment. They prevent packet loss and help maintain hight throughput. As bandwidths have increased so have the buffer sizes. In some cases way to much. This, and the fact that Active Queue Management (AQM) is seldom implemented, has given rise to a phenomenon called Bufferbloat.

    Bufferbloat is manifested at the bottleneck of the network path by large flows creating standing queues that choke out smaller, and usually delay-sensitive, flows. Since the bottleneck is often located at the consumer edge, this is where the focus of this thesis lies.

    This work evaluates three different AQM solutions that lower delays without requiring complicated configuration; CoDel, FQ_CoDel and PIE. FQ_CoDel had the best performance in the tests, with the lowest consistent delays and high throughput. This thesis recommends that AQM is implemented at the network edge, preferably FQ_CoDel.

  • 14.
    Degerfält, Per
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Strömberg, Niklas
    Mälardalen University, School of Innovation, Design and Engineering.
    Programmering av styrning av tvättarm på tvättrobot.2008Independent thesis Advanced level (degree of Magister), 20 points / 30 hpStudent thesis
    Abstract [en]

    Ramsta Robotics är ett företag som ligger i Uppsala. Företaget grundades 1999 av tre uppfinnare. Man har utvecklat en robot, som används för att göra rent i djurstallar. Tvättarbetet har hittills gjorts helt manuellt med högtryckstvätt. I framför allt svinhus är

    arbetsmiljön direkt hälsovådlig – bland annat på grund av alla de kväveföreningar som löses ut när vattnet blöter upp anläggningen. Principen för roboten är att man lär den genom att med en styrpanel styra en arm så att alla ytor i boxen blir besprutad med högtryckstvätten minst en gång. Hela förloppet spelas in, och sedan kan roboten spela upp programmet flera gånger, och på det sättet kan roboten på egen hand göra rent i ett antal boxar, som står efter varandra.

    Affärsidén har varit att utveckla en prisvärd robot där datastödet utgörs av ett enkelt styr- och reglersystem för industrin, en s.k. PLC. Den styr via ett drivkort 5-6 motorer, dock bara en motor i taget. Den traditionella robotteknikens komplexa mekanik och höga prisnivåer gör det direkt omöjligt att sätta in denna teknikplattform i jordbrukssammanhang. Kraven på en tvättrobot när det gäller mikrometerprecision och hastighet är heller inte lika hög som hos mer traditionella robotar.

    Idag säljs detta system i ett flertal länder i Europa och också i Kanada. Hittills har c:a 150 robotar sålts, de flesta för att användas i svinproduktion men även fågel produktion och annan

    industri har visat sig vara en marknad. C:a 100 maskiner är sålda i Sverige som representerar c:a 0,3 % av världens produktion av fläskkött. Eftersom Sverige är en så liten marknad i agrara sammanhang är verksamheten idag främst inriktad på export. Verksamheten är expanderande och företaget sysselsätter idag 4 personer på kontoret i Uppsala förutom tillverkning och service som köps externt. Omsättningen 2005 var c:a 8 milj. kronor och beräknas för 2006 närma sig 15 milj.

    I samarbete med Robotdalen kommer fem olika examensarbeten på Mälardalens högskola att ge ett ökat tekniskt innehåll i företagets olika lösningar.

    Projektbeskrivning:

    Med individuella styrkort på respektive motor är det möjligt att använda en helt annan teknik för styrningen av motorerna på robotarmen. Man kan gå från att styra respektive led till att

    utnyttja invers kinematik, och användaren styr var munstycket ska vara beläget, och styrprogrammet omvandlar den önskade positionen till vinklar och lägen för respektive led.

    Att bygga ett komplett styrsystem kan vara ganska omfattande, men avsikten med detta examensarbete är att göra en första version av styrprogram, där användaren kanske kör fram armen till en punkt på en yta som ska tvättas, och sedan till en andra punkt, till en tredje.

    Dessa tre punkter definierar en triangel på samma sätt som man bygger upp ytor i OpenGL.

    En fjärde punkt ger med punkterna två och tre ytterligare en triangel. När sedan en hel yta har ’ritats upp’ (för en rak rektangel är det endast två trianglar) ska programmet kunna styra ut

    robotarmens rörelsemönster.

  • 15.
    Dunkels, Adam
    Swedish Institute of Computer Science.
    Full TCP/IP for 8-bit Architectures2003In: MobiSys '03 Proceedings of the 1st international conference on Mobile systems, applications and services, 2003, p. 85-98Conference paper (Refereed)
    Abstract [en]

    We describe two small and portable TCP/IP implementations fulfilling the subset of RFC1122 requirements needed for full host-to-host interoperability. Our TCP/IP implementations do not sacrifice any of TCP's mechanisms such as urgent data or congestion control. They support IP fragment reassembly and the number of multiple simultaneous connections is limited only by the available RAM. Despite being small and simple, our implementations do not require their peers to have complex, full-size stacks, but can communicate with peers running a similarly light-weight stack. The code size is on the order of 10 kilobytes and RAM usage can be configured to be as low as a few hundred bytes.

  • 16.
    Dunkels, Adam
    et al.
    Swedish Institute of Computer Science, Sweden.
    Schmidt, Oliver
    Voigt, Thiemo
    Swedish Institute of Computer Science, Sweden.
    Using Protothreads for Sensor Node Programming2005In: Proceedings of the REALWSN 2005 Workshop on Real-World Wireless Sensor Networks (2005), 2005Conference paper (Refereed)
  • 17.
    Dunkels, Adam
    et al.
    Swedish Institute of Computer Science, Sweden.
    Voigt, Thiemo
    Swedish Institute of Computer Science, Sweden.
    Alonso, Juan
    Swedish Institute of Computer Science, Sweden.
    Making TCP/IP viable for wireless sensor networks2004Conference paper (Refereed)
    Abstract [en]

    The TCP/IP protocol suite, which has proven itself highly successful in wired networks, is often claimed to be unsuited for wireless micro-sensor networks. In this work, we question this conventional wisdom and present a number of mechanisms that are intended to enable the use of TCP/IP for wireless sensor networks: spatial IP address assignment, shared context header compression, application overlay routing, and distributed TCP caching (DTC). Sensor networks based on TCP/IP have the advantage of being able to directly communicate with an infrastructure consisting either of a wired IP network or of IP-based wireless technology such as GPRS. We have implemented parts of our mechanisms both in a simulator environment and on actual sensor nodes. Our preliminary results are promising.

  • 18.
    Elgström, Dennis
    Mälardalen University, School of Innovation, Design and Engineering.
    Implementation of secure network solutions for Project Area2014Independent thesis Basic level (university diploma), 180 HE creditsStudent thesis
  • 19.
    Fersman, Elena
    et al.
    Uppsala University, Sweden.
    Krcal, Pavel
    Uppsala University, Sweden.
    Pettersson, Paul
    Mälardalen University, Department of Computer Science and Electronics. Uppsala University, Sweden.
    Yi, Wang
    Uppsala University, Sweden.
    Task Automata: Schedulability, Decidability and Undecidability2007In: International Journal of Information and Computation, ISSN 0890-5401, Vol. 205, p. 1149-1172Article in journal (Refereed)
    Abstract [en]

    We present a model, task automata, for real time systems with non-uniformly recurring computation tasks. It is an extended version of timed automata with asynchronous processes that are computation tasks generated (or triggered) by timed events. Compared with classical task models for real time systems, task automata may be used to describe tasks (1) that are generated non-deterministically according to timing constraints in timed automata, (2) that may have interval execution times representing the best case and the worst case execution times, and (3) whose completion times may influence the releases of task instances. We generalize the classical notion of schedulability to task automata. A task automaton is schedulable if there exists a scheduling strategy such that all possible sequences of events generated by the automaton are schedulable in the sense that all associated tasks can be computed within their deadlines. Our first technical result is that the schedulability for a given scheduling strategy can be checked algorithmically for the class of task automata when the best case and the worst case execution times of tasks are equal. The proof is based on a decidable class of suspension automata: timed automata with bounded subtraction in which clocks may be updated by subtractions within a bounded zone. We shall also study the borderline between decidable and undecidable cases. Our second technical result shows that the schedulability checking problem will be undecidable if the following three conditions hold: (1) the execution times of tasks are intervals, (2) the precise finishing time of a task instance may influence new task releases, and (3) a task is allowed to preempt another running task.

  • 20.
    Fersman, Elena
    et al.
    Uppsala University, Sweden.
    Mokrushin, Leonid
    Uppsala University, Sweden.
    Pettersson, Paul
    Uppsala University, Sweden.
    Yi, Wang
    Uppsala University, Sweden.
    Schedulability Analysis of Fixed Priority Systems using Timed Automata2006In: Theoretical Computer Science, ISSN 0304-3975, E-ISSN 1879-2294, Vol. 354, no 2, p. 301-317Article in journal (Refereed)
    Abstract [en]

    In classic scheduling theory, real-time tasks are usually assumed to be periodic, i.e. tasks are released and computed with fixed rates periodically. To relax the stringent constraints on task arrival times, we propose to use timed automata to describe task arrival patterns. In a previous work, it is shown that the general schedulability checking problem for such models is a reachability problem for a decidable class of timed automata extended with subtraction. Unfortunately, the number of clocks needed in the analysis is proportional to the maximal number of schedulable task instances associated with a model, which is in many cases huge. In this paper, we show that for fixed-priority scheduling strategy, the schedulability checking problem can be solved using standard timed automata with two extra clocks in addition to the clocks used in the original model to describe task arrival times. The analysis can be done in a similar manner to response time analysis in classic Rate-Monotonic Analysis (RMA). The result is further extended to systems with data-dependent control, in which the release time of a task may depend on the time-point at which other tasks finish their execution. For the case when the execution times of tasks are constants, we show that the schedulability problem can be solved using n+1 extra clocks, where n is the number of tasks. The presented analysis techniques have been implemented in the Times tool. For systems with only periodic tasks, the performance of the tool is comparable with tools implementing the classic RMA technique based on equation-solving, without suffering from the exponential explosion in the number of tasks.

  • 21.
    Fogel, Johan
    Mälardalen University. Mälardalen University, School of Innovation, Design and Engineering.
    IP version 6 in larger city networks and at Internet service providers2009Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Since the 90ies a bunch of problems and flaws in the old Internet Protocol version four has occurred.The biggest problem is the extinction of addresses which will come soon, soon in the matter of theclassic “wolf is coming” matter, but as in the fairy tale the wolf will finally come. When this will happenis unknown, but not many believes it won’t. Carl-Henrik Swanberg CEO for Ericsson once said that year2020 there will be 50 billion mobile units connected to internet. Considering there is maximum 4 billionaddresses in IPv4 the needs for more addresses will be significant. The solution of this is the version sixof Internet Protocol released in middle of the 90ies. This thesis mentions a lot of the problems with theold version and tries to make a good explanation of the benefits and possibilities that lies within thenew. It also contains a larger amount of information on the protocols that lies within this, like newversion of OSPF, the extensions of BGPv4 called multiprotocol BGP (MP-BGP) and new things likenetwork discovery protocol (NDP). The later chapter is about the planning of an implementation atMälarenergi City Network and the implementation at the internet service provider MDFnet whichnowadays runs IPv6 in their core and office network.

  • 22.
    Forsberg, Andreas
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Larsson, Christoffer
    Mälardalen University, School of Innovation, Design and Engineering.
    Vidareutveckling av PROFIBUS-modul2010Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This report describes a master thesis which was done at the company Motion Control i Västerås AB. The report follows the project development stages and describes how the process of developing electronics and embedded software for a communication module has progressed. The purpose of the communication module is to serve as a link between a controller and an I/O device.

     

    The initial parts of the report consist of studies about the communication protocols PROFIBUS and PROFINET which are standard communication methods in the industry. The studies formed the basis for which protocol to be used in the module. PROFIBUS was chosen and a module was designed based on the determined requirements. Furthermore, the report describes how the hardware and firmware have been developed. The module was tested to verify that all requirements were met.

     

    Overall the project was successful and after some minor hardware changes the module could be used in products where PROFIBUS communication is desired.

  • 23.
    Girs, Svetlana
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Uhlemann, Elisabeth
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Björkman, Mats
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Adopting FEC and Packet Combining to Increase the Performance of IWSNs Using Relaying2016In: International Conference on Computing and Network Communications CoCoNet'15, 2016, p. 90-97Conference paper (Refereed)
    Abstract [en]

    Industrial networks can benefit significantly from introduction of wireless communication. However, wireless systems suffer from much higher packet error rates than wired networks do, making it difficult to obtain sufficient reliability within application deadlines. One promising approach to increase the reliability of wireless communication systems without causing excessive additional delays is to exploit spatial diversity. However, often in industrial networks it is not possible to place the relay nodes optimally. Due to this not even relay nodes located close to the source are able to receive the source packets missing at the destination correctly and consequently they cannot assist by relaying. Therefore, to benefit even further from relaying, additional measures should be taken both to increase the number of the correct packets at the relay nodes and to allow the destination to recover more correct packets. Consequently, the focus of this work is schemes enabling relaying, forward-error-correction (FEC) and packet combining without causing additional delays or complexity such that it is possible to use off the shelf transceivers. The results show that the introduction of FEC and packet combining does improve performance by enabling relay nodes to help more often. However, the exact gain depends on the specific FEC scheme used and, in particular, the size of the preamble and other fields that must be left uncoded, but still be received correctly, to be able to use FEC on the received packet.

  • 24.
    Hansen, Ewa
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Neander, Jonas
    Mälardalen University, Department of Computer Science and Electronics.
    Nolin, Mikel
    Mälardalen University, Department of Computer Science and Electronics.
    Björkman, Mats
    Mälardalen University, Department of Computer Science and Electronics.
    Energy-Efficient Cluster Formation for Large Sensor Networks using a Minimum Separation Distance2006In: In proceedings of the Fifth Annual Mediterranean Ad Hoc Networking Workshop, 2006Conference paper (Refereed)
  • 25.
    Hansen, Ewa
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Neander, Jonas
    Mälardalen University, Department of Computer Science and Electronics.
    Sjödin, Mikael
    Mälardalen University, Department of Computer Science and Electronics.
    Björkman, Mats
    Mälardalen University, Department of Computer Science and Electronics.
    Energy-Efficient Cluster Formation for Large Sensor Networks using a Minimum Separation Distance2006In: Proceedings of The Fifth Annual Mediterranean Ad Hoc Networking Workshop (Med-Hoc-Net 2006), 2006Conference paper (Refereed)
    Abstract [en]

    In this paper we investigate the usefulness of enforcing a minimum separation distance between cluster heads in a cluster based sensor network, thereby prolonging network lifetime by spreading the cluster heads, thus lowering the average communication energy consumption.

    We have performed initial simulations in order to determine how much we can lower the energy consumption in the sensor network by separating the cluster heads. We have also investigated how the number of clusters affect the energy consumption for a given minimum separation distance.

    The results show that our sensor network performs up to 150% better when introducing a minimum separation distance between cluster heads, comparing the number of messages received at the base station.

    The simulations also show that the minimum separation distance resulting in the lowest energy consumption in our network varies with the number of clusters.

  • 26.
    Holmqvist, Johan
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Karlsson, Tord
    Mälardalen University, School of Innovation, Design and Engineering.
    Enhanced Automotive Real-Time Testing Through Increased Development Process Quality2010Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The purpose of this master thesis is to improve the quality of software testing in a large company developing real-time embedded systems. Software testing is a very important part of software development. By performing comprehensive software testing the quality and validity of a software system can be assured. One of the main issues with software testing is to be sure that the tests are correct. Knowing what to test, but also how to perform testing, is of utmost importance.

    In this thesis, we explore different ways to increase the quality of real-time testing by introducing new techniques in several stages of the software development model. Four complementary methods are suggested. The proposed methods are validated by implementing them in an existing and completed project on a subset of the software development process. The original output from the completed project is compared with the new output.

    The presented results from the validation are positive in the sense that it is shown that the test stage was more qualitative, mostly due to a higher level of quality on input from earlier stages.

  • 27.
    Hosseini, Seyed Morteza
    Mälardalen University, School of Innovation, Design and Engineering.
    A Model for Estimating the ExecutionCost of Test Cases2015Independent thesis Advanced level (degree of Master (Two Years)), 10 credits / 15 HE creditsStudent thesis
  • 28.
    Huu, Tung Pham
    et al.
    NUCE, Fac Informat Technol, 55 Giai Phong Rd, Hanoi, Vietnam.
    Quach, Truong Xuan
    TNU Univ Informat & Commun Technol, Ho Chi Minh City, Vietnam.
    Tran, Hung Vinh
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Zepernick, Hans-Jurgen
    Blekinge Inst Technol, Karlskrona, Sweden..
    Sibomana, Louis
    Univ Rwanda, Kigali, Rwanda..
    On Proactive Attacks for Coping With Cooperative Attacks in Relay Networks2017In: 2017 23RD ASIA-PACIFIC CONFERENCE ON COMMUNICATIONS (APCC): BRIDGING THE METROPOLITAN AND THE REMOTE, IEEE , 2017, p. 220-225Conference paper (Refereed)
    Abstract [en]

    Cooperative communications in which relays assist the transmission of signals from source to destination offer extended radio coverage and improved link reliable. However, transmitting signals with the help of a relay network may also open additional avenues for eavesdropper to overhear confidential information. Further, as jammers and eavesdroppers may cooperate to attack the relay network, offering secure communications becomes a challenging problem. To cope and reduce the effect of such cooperative attacks, we propose a proactive attack scheme in which the legitimate users generate jamming signals in an attempt to counteract such hostile cooperative attacks. In order to assess the security performance of the proactive attack scheme compared to a non-protection scheme, an analytical expression of the secrecy outage probability is derived. Numerical results for different system settings are provided showing that the proactive attack scheme can indeed significantly improve the security performance of the considered relay networks.

  • 29.
    Inam, Rafia
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Cederman, Daniel
    Department of Computing Science and Engineering, Chalmers University.
    Tsigas, Philippas
    Department of Computing Science and Engineering, Chalmers University.
    A* Algorithm for Graphics Processors2010In: THIRD SWEDISH WORKSHOP ON MULTI-CORE COMPUTING - MCC'10, Chalmers University of Technology, Sweden, 2010Conference paper (Refereed)
    Abstract [en]

    Today's computer games have thousands of agents moving at the same time in areas inhabited by a large number of obstacles. In such an environment it is important to be able to calculate multiple shortest paths concurrently in an efficient manner. The highly parallel nature of the graphics processor suits this scenario perfectly. We have implemented a graphics processor based version of the A* path finding algorithm together with three algorithmic improvements that allow it to work faster and on bigger maps. The first makes use of pre-calculated paths for commonly used paths. The second use multiple threads that work concurrently on the same path. The third improvement makes use of a scheme that hierarchically breaks down large search spaces. In the latter the algorithm first calculates the path on a high level abstraction of the map, lowering the amount of nodes that needs to be visited. This algorithmic technique makes it possible to calculate more paths concurrently on large map settings compared to what was possible using the standard A* algorithm. Experimental results comparing the efficiency of the algorithmic techniques on a NVIDIA GeForce GTX 260 with 24 multi-processors are also presented in the paper.

  • 30.
    Johansson, Henrik
    Mälardalen University, School of Innovation, Design and Engineering.
    Evaluating Vivado High-Level Synthesis on OpenCV Functions for the Zynq-7000 FPGA2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    More complex and intricate Computer Vision algorithms combined with higher resolution image streams put bigger and bigger demands on processing power. CPU clock frequencies are now pushing the limits of possible speeds, and have instead started growing in number of cores. Most Computer Vision algorithms' performance respond well to parallel solutions. Dividing the algorithm over 4-8 CPU cores can give a good speed-up, but using chips with Programmable Logic (PL) such as FPGA's can give even more.

    An interesting recent addition to the FPGA family is a System on Chip (SoC) that combines a CPU and an FPGA in one chip, such as the Zynq-7000 series from Xilinx. This tight integration between the Programmable Logic and Processing System (PS) opens up for designs where C programs can use the programmable logic to accelerate selected parts of the algorithm, while still behaving like a C program.

    On that subject, Xilinx has introduced a new High-Level Synthesis Tool (HLST) called Vivado HLS, which has the power to accelerate C code by synthesizing it to Hardware Description Language (HDL) code. This potentially bridges two otherwise very separate worlds; the ever popular OpenCV library and FPGAs.

    This thesis will focus on evaluating Vivado HLS from Xilinx primarily with image processing in mind for potential use on GIMME-2; a system with a Zynq-7020 SoC and two high resolution image sensors, tailored for stereo vision.

  • 31.
    Johnsson, Andreas
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Björkman, Mats
    Measuring the Impact of Active Probing on TCP2006Conference paper (Other academic)
    Abstract [en]

    Available bandwidth measurement methods have be- ome more and more a epted to be used when seeking the status of a network path. To measure the end-toend available bandwidth without a ess to the path routers, these methods inje t UDP based probe pa kets into the network path. The probe-pa ket load an transiently be high and thus it is important to study the impa t on the existing network ows. In this paper, we show and dis uss our simulation results on how the TCP ows are ae ted when inje ting probe pa kets with dierent ight patterns into the network path. We investigate the relation between the amount of inje ted probe pa kets and the redu tion in TCP performan e. Further, we suggest a quantitative denition of the term network friendly probing.

  • 32.
    Johnsson, Andreas
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Björkman, Mats
    Mälardalen University, Department of Computer Science and Electronics.
    Measuring the Impact of Active Probing on TCP2006Conference paper (Refereed)
    Abstract [en]

    Available bandwidth measurement methods have become more and more accepted to be

    used when seeking the status of a network path. To measure the end-to-end available bandwidth without access to the path routers, these methods inject probe packets into the network path. The probe-packet load can transiently be high and thus it is important to study the impact on the existing TCP flows.

    In this paper, we show and discuss our simulation results on how the TCP flows are affected when injecting probe packets with different flight patterns into the network path. We also investigate the relation between the amount of injected probe packets and the reduction in TCP performance. Finally we suggest and discuss a quantitative definition of the term ``network friendly probing''.

  • 33.
    Johnsson, Andreas
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Björkman, Mats
    On measuring the available bandwidth in wireless 802.11b networksManuscript (Other academic)
  • 34.
    Johnsson, Andreas
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Melander, Bob
    Björkman, Mats
    Mälardalen University, Department of Computer Science and Electronics.
    On the Analysis of Packet-Train Probing Schemes2004Conference paper (Other academic)
    Abstract [en]

    With a better understanding of how probe packets and cross-traffic packets interact with each other, more accurate measurement methods based on active probing can be developed. Several existing measurement methods rely on packet-train probing schemes. In this article, we study and describe the interactions between probe packets and cross-traffic packets. When one packet within a packet train is delayed, the dispersion (i.e. packet separation) of at least two (and possibly more) probe packets will change. Furthermore, the dispersions are not independent, which may bias calculations based on statistical operations. Many methods use dispersion averages, such as the mean, in the calculation of bandwidth estimates and predictions. We describe cross traffic effects on packet trains. The interaction results in mirror, chain and quantifi- cation patterns. Experiments have been performed in a testbed to explore these patterns. In histograms of delay variations for adjacent probe packets, these patterns are manifested as different identifiable signatures. Finally, we also discuss the effect of these patterns on the mean and median operations.

  • 35.
    Jägemar, Marcus
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Ericsson, Sweden.
    Utilizing Hardware Monitoring to Improve the Performance of Industrial Systems2016Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    The drastically increasing use of Information and Communications Technology has resulted in a growing demand for network capacity. In this Licentiate thesis, we show how to monitor, model and finally improve network performance for large industrial systems. We also show how to use modeling techniques to move performance testing to an earlier design phase, with the aim to reduce the total development time of large systems. Our first contribution is a low-intrusive method for long-term hardware characteristic measurements of production nodes located at customer sites. Our second contribution is a technique to mimic the hardware usage of a production environment by creating a characteristics model. The cloned environment makes function test suites more realistic. The goal when creating the model is to reduce the system development time by moving late-stage performance testing to early design phases thereby improving the quality of the test environment. The third and final contribution is a network performance improvement where we dynamically trade computational capacity for a message round-trip time reduction when there are CPU cycles to spare. We have implemented an automatic feedback controlled mechanism for transparent message compression resulting in improved messaging performance between interconnected network nodes. Our mechanism continuously evaluates eleven compression algorithms on message stream content and network congestion level. The message subsystem will use the compression algorithm that provides the lowest messaging time. If the message content or network load change, a new evaluation is performed. We have conducted several case studies in an industrial environment and verified all contributions on a large telecommunication system manufactured by Ericsson. System engineers frequently use the monitoring and modeling functionality for debugging purposes in production environments. We have deployed all techniques in a complicated industrial legacy system with minimal impact. We show that we can provide not only a solution but a cost-effective solution, which is an important requirement for industrial systems.

  • 36.
    Jägemar, Marcus
    et al.
    Ericsson, Stockholm, Sweden.
    Eldh, Sigrid
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ermedahl, Andreas
    Ericsson, Stockholm, Sweden.
    Lisper, Björn
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Automatic Message Compression with Overload Protection2016In: Journal of Systems and Software, ISSN 0164-1212, E-ISSN 1873-1228, Vol. 121, no 1 nov, p. 209-222Article in journal (Refereed)
    Abstract [en]

    In this paper, we show that it is possible to increase the message throughput of a large-scale industrial system by selectively compress messages. The demand for new high-performance message processing systems conflicts with the cost effectiveness of legacy systems. The result is often a mixed environment with several concurrent system generations. Such a mixed environment does not allow a complete replacement of the communication backbone to provide the increased messaging performance. Thus, performance-enhancing software solutions are highly attractive. Our contribution is 1) an online compression mechanism that automatically selects the most appropriate compression algorithm to minimize the message round trip time; 2) a compression overload mechanism that ensures ample resources for other processes sharing the same CPU. We have integrated 11 well-known compression algorithms/configurations and tested them with production node traffic. In our target system, automatic message compression results is a 9.6% reduction of message round trip time. The selection procedure is fully automatic and does not require any manual intervention. The automatic behavior makes it particularly suitable for large systems where it is difficult to predict future system behavior.

  • 37.
    Jägemar, Marcus
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Ericsson, Stockholm, Sweden.
    Lisper, Björn
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Eldh, Sigrid
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ermedahl, Andreas
    Ericsson, Stockholm, Sweden.
    Andai, Gabor
    Automatic Benchmarking for Early-Stage Performance Verification of Industrial Systems2016Manuscript (preprint) (Other academic)
  • 38.
    Karlström, Daniel
    Mälardalen University, School of Innovation, Design and Engineering.
    Implementation of data-collection tools using NetFlow for statistical analysis at the ISP level2012Independent thesis Basic level (professional degree), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    Defending against Dos- and DDoS attacks is difficult to accomplish; finding and filtering out illegitimate traffic from the legitimate flow is near impossible. Taking steps to mitigate or even block the traffic can only be done once the IP addresses of the attackers are known. This is achievable by monitoring the flows to- and from the target and identifying the attacker's IP addresses, allowing the company or their ISP to block the addresses itself by blackholing them (also known as a null route).

    Using the IP accounting and monitoring tool “pmacct”, this thesis aims to investigate whether or not the pmacct suite is suited for larger installations when tracking and mitigating DDoS-attacks, such at an Internet Service Provider (ISP). Potential problems are the amount of traffic that need to be analyzed and the computational power required to do it. This thesis also provide information about the pmacct suite at large.

    The conclusions are positive, indicating it does scale up to handle larger installations when given careful consideration and planning.

  • 39.
    Khalilzad, Nima
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Adaptive and Flexible Scheduling Frameworks for Component-Based Real-Time Systems2015Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Modern computer systems are often designed to play a multipurpose role. Therefore, they are capable of running a number of software components (software programs) simultaneously in parallel. These software components should share the system resources (e.g. processor and network) such that all of them run and finish their computations as expected. On the other hand, a number of software components have timing requirements meaning that they should not only access the resources, but this access should also be in a timely manner. Thus, there is a need to timely share the resources among different software components. The time-sharing is often realized by reserving a time-portion of resources for each component. Such a reservation should be adequate and resource-efficient. It should be sufficient to preserve the timing properties of the components. Also, the reservations should be resource-efficient to reduce the components' footprint on the resources which in turn allows integration of more software components on a given hardware resource. In this thesis, we mainly focus on the resource-efficiency of the reservations. We consider two cases. (I) Components which can tolerate occasional timing violations (soft real-time components): in this case we adjust the reservations during run-time to match the reservation sizes based on the instantaneous requirements of the components. (II) Components which cannot tolerate any timing violations (hard real-time components): in this case we use flexible approaches which allow us to improve the resource-efficiency at the design time.

  • 40.
    Khalilzad, Nima
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ashjaei, Mohammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Almeida, Luis
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. IT/DEEC/University of Porto, Portugal.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Adaptive Multi-Resource End-to-End Reservations for Component-Based Distributed Real-Time Systems2015In: ESTIMedia 2015 - 13th IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2015, p. Article number 7351772-Conference paper (Refereed)
    Abstract [en]

    Complexity in the real-time embedded softwaredomain has been growing rapidly. The component-based softwaredevelopment approach facilitates the development process of suchsoftware systems by dividing a complex system into a numberof simpler components. Resource reservation techniques havebeen widely used for providing resources to real-time softwarecomponents. In this paper we target real-time components operatingon a distributed resource infrastructure. Furthermore,we target a class of software components which demonstratedynamic resource consumption behavior. A prime example ofsuch components is a multimedia software component. In thepaper, we present a framework supporting multi-resource endto-end resource reservations. We reserve resource bandwidths onboth processor resources as well as on the network resources. Theproposed framework utilizes a Multiple Input Multiple Output(MIMO) controller which adjusts the sizes of reservations trackingthe dynamic resource demands of the software components. Finally, we present a case study using a multimedia component todemonstrate the performance and efficiency of our framework.

  • 41.
    Khalilzad, Nima
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    An Adaptive Scheduling Framework for Component-Based Real-Time Systems2015Report (Other academic)
  • 42.
    Khalilzad, Nima
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Behnam, Moris
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Nolte, Thomas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    On Component-Based Software Development for Multiprocessor Real-Time Systems2015In: Proceedings - IEEE 21st International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2015, 2015, p. 132-140Conference paper (Refereed)
    Abstract [en]

    Component-based software development providesa modular approach to develop complex software systems. In the context of real-time systems, it is desirable to abstract the timing properties of software components using an interface foreach component. The timing properties of the whole system, composed of multiple components, is studied using the component interfaces. In this paper we focus on periodic interface models. In the case of components developed for single processor platforms, for examining the system schedulability, the interfaces can be regarded as periodic tasks. Thus, making it possible to use the conventional schedulability analyses for the system level schedulability test. In the case of components developed formultiprocessors, since interfaces may have utilization larger than 100 % of a single processor, it is not possible to directly use the component interfaces for the system schedulability test. There-fore, the interfaces have to be decomposed before performing thesystem level schedulability test. In this paper, we target the special case of partitioned EDF for scheduling the components integrated on a multiprocessor. Therefore, the system level schedulability test is equivalent to finding a feasible allocation of component interfaces on the multiprocessor. We propose two algorithms for allocating the multiprocessor periodic interfaces. In addition, we propose anorthogonal approach for developing component-based real-timesystems on multiprocessors in which components with utilizationmore than 100 % of a single processor are divided into smaller subcomponents before abstracting their interfaces. We show, through extensive evaluations, that our alternative approach significantly reduces the interface overhead.

  • 43.
    Larsson, Thomas
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Akenine-Möller, Tomas
    Lund University, Sweden.
    Lengyel, Eric
    Terathon Software.
    On Faster Sphere-Box Overlap Testing2007In: Journal of graphics tools, ISSN 2165-347X, Vol. 12, no 1, p. 3-8Article in journal (Refereed)
    Abstract [en]

    We present faster overlap tests between spheres and either axis-aligned or oriented boxes. By utilizing quick rejection tests, faster execution times are observed compared to previous techniques. In addition, we present alternative vectorized overlap tests, which are compared to the sequential algorithms. Source code is available online.

  • 44.
    Lenander, Per
    et al.
    Mälardalen University, School of Innovation, Design and Engineering.
    Fosselius, Anton
    Mälardalen University, School of Innovation, Design and Engineering.
    ORGFX: a Wishbone compatible Graphics Accelerator for the OpenRISC processor2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Modern embedded systems such as cellphones or medical instrumentation use increasingly complex graph-ical interfaces. Currently there are no widely used open hardware solutions to accelerate embedded graphicalapplications. This thesis presents the ORSoC graphics accelerator (ORGFX), an open hardware graphics ac-celerator that can be used with programmable hardware. A standalone software implementation is providedto help for a quick development of accelerated applications.The accelerator is able to render 2D, 3D and vector graphics. The example implementation of theORGFX is integrated with the OpenRISC Reference Platform System on Chip version 2 (ORPSoCv2). Thenal implementation runs on a Xilinx FPGA at 50 MHz, and provides accelerated graphics output froman HDMI port. An extensive software driver and a set of utilities to ease development for the graphicsaccelerator are provided along with the hardware. The software implementation of the accelerator uses thesame API as the hardware drivers, making it possible to quickly develop applications for the acceleratorwithout access to a physical platform.The nal implementation trades performance against platform independence and generality. The com-ponent can be integrated with any CPU or memory chip and works alongside a custom display core thatrenders the output to an external screen. The software drivers can be run bare metal or modied to run onan operating system.All of the hardware and software developed in this project is provided as open source under the GNULesser General Public License (LGPL), and can be downloaded from www.opencores.com. The authorshope that future releases will be integrated as a standard component into the OpenRISC Reference PlatformSystem on Chip.

  • 45.
    Lindhult, Johan
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Lisper, Björn
    Mälardalen University, Department of Computer Science and Electronics.
    Sequential PLEX, and its Potential for Parallel Execution2007Conference paper (Refereed)
    Abstract [en]

    Some computer systems have been designed under the assumption that activities in the system are executed non-preemptively. Exclusive access to any shared data in such a system is automatically guaranteed as long as the system is executed on a single-processor architecture. However, if the activities are executed on a multiprocessor, exclusive access to the data must be guaranteed when memory con- flicts are possible. An analysis of the potential memory conflicts can be used to estimate the possibility for parallel execution. Central parts of the AXE telephone exchange system from Ericsson is programmed in the language PLEX. The current software is executed on a single-processor architecture, and assumes non-preemptive execution. In this paper, we investigate some existing PLEX code with respect to the number of possible shared-memory conflicts that could arise if the existing code, without modifications, would be executed on a parallel architecture. Our initial results are promising; only by examining the data that actually can be shared, we manage to reduce the number of conflicts from the assumed 100% to figures between 25-75% for the observed programs. Simple optimizations decrease the numbers even further.

  • 46. Lo Bello, Lucia
    et al.
    Kaczynski, Giordano A.
    Nolte, Thomas
    Mälardalen University, Department of Computer Science and Electronics.
    Sorbello, Gino
    Sgro, Francesco
    Mirabella, Orazio
    An approach to support UAV to ground station real-time communications in a land monitoring system2006Conference paper (Refereed)
  • 47.
    Lu, Yue
    Mälardalen University, School of Innovation, Design and Engineering.
    Approximation Techniques for Timing Analysis of Complex Real-Time Embedded Systems2010Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    To date, many industrial embedded systems are very large, flexible, and highly configurable software systems, containing millions of lines of code and consisting of hundreds of tasks, many with real-time constraints, being triggered in complex, nested patterns. Furthermore, the temporal dependencies between tasks in such systems are difficult to determine analytically, and they vary the execution time and response time of tasks greatly. We refer to such systems as Complex Real-Time Embedded Systems (CRTES).

    To maintain, analyze and reuse such CRTES is very difficult and expensive, which, nevertheless, offers high business value in response to great concern in industry. Moreover, in such context, not only the functional behavior of systems has to be assured, but also non-functional properties such as the temporal behavior, i.e., Worst-Case Response Time (WCRT) of the adhering tasks in systems has to be known. However, due to high complexity of such systems and the nature of the problem, the exact WCRT of tasks is impossible to find in practice, but may only be bounded. In addition, the existing relatively well-developed theories for modeling and analysis of real-time systems are having problems, which limit their application in the context. In this thesis, we address this challenge, and present a framework for approximate timing analysis of CRTES that provides a tight interval of WCRT estimates of tasks by the usage of three novel contributions.

    The first contribution is a novel statistical approach to WCRT analysis of CRTES. The proposed algorithm combines Extreme Value Theory (EVT) with other statistical methods in order to produce a probabilistic WCRT estimate, using response time data from either Monte Carlo simulations of a detailed model of the system, or time-stamped traces of the real system execution. The focus of the method is to give a WCRT prediction with a given probability of being exceeded, which potentially could be considered as an upper bound on the WCRT estimate in systems, especially in the case where conventional timing analysis methods cannot be applied.

    The second contribution is to introduce a concrete process of formally obtaining the exact value of both Worst-Case Execution Time (WCET) and WCRT of tasks in the system model by using upper-part binary search algorithms together with a timed model checker, after a semantic-preserving model transformation. The underline premise is that the size and complexity of CRTES have to be reduced such that they can be manageable by the model checking tool.

    The third contribution is to apply an optimization algorithm, in this case a meta-heuristic search algorithm, on top of the traditional Monte Carlo simula-tion, which yields substantially better results with respect to tight lower bounds on WCRT estimates of tasks in CRTES.

    In addition, a number of tools have been implemented and used for the evaluation of the research results. These evaluations, using four simulation models depicting two fictive but representative industrial control applications, give clear indication that the proposed methods have the potential to be both applicable and useful in practice.

  • 48.
    Lundin, Jonatan
    Mälardalen University, School of Innovation, Design and Engineering, Innovation and Product Realisation.
    Towards a normative conceptual framework for information-seeking studies in technical communication2014In: ISDOC '14: Proceedings of the International Conference on Information Systems and Design of Communication, 2014, p. 15-19Conference paper (Refereed)
    Abstract [en]

    The article proposes a conceptual framework supporting researchers in technical communication when using participant observation to collect data on users' information-seeking behaviors, such as what type of information users need in a work task context. The proposed framework is a synthesis, combining and integrating systemic-structural theory of activity and Byström and Hansen conceptual framework.

  • 49.
    Malm, Jean
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Skoog, Jonas
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Analysing the transformability from Action Language for fUML to ALF2015Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    Graphical modelling languages, such as UML, are commonly used by software developers to plan and design larger systems. In order to test these designs, executable models such as foundational UML utilizing the action language Alf have been introduced. This added functionality makes it possible to analyse the system during the design phase. One type of analysis that may be of interest is the flow analysis. One way of performing such an analysis is through the use of the SWEET (SWEdish Execution Time) tool, developed at Mälardalen University.SWEET requires code to be in the intermediate language ALF (not to be confused with Alf for modelling), so in order to perform a flow analysis during the design phase of a system, the textual modelling language Alf has to be translated to the intermediate language for flow analysis ALF.

    This paper begins by presenting the problem and background of performing such a translation and continues by describing the methods used to determine a subset of Alf suited for translation. The proposed translation is finally validated through the (manual) translation and verification of a case study.

  • 50.
    Neander, Jonas
    et al.
    Mälardalen University, Department of Computer Science and Electronics.
    Hansen, Ewa
    Mälardalen University, Department of Computer Science and Electronics.
    Mäki-Turja, Jukka
    Mälardalen University, Department of Computer Science and Electronics.
    Sjödin, Mikael
    Mälardalen University, Department of Computer Science and Electronics.
    Björkman, Mats
    Mälardalen University, Department of Computer Science and Electronics.
    Prolonging Network Lifetime in Long Distance Sensor Networks using a TDMA Scheduler2006Conference paper (Refereed)
    Abstract [en]

    In this paper we present a Time Division Multiple Access (TDMA) scheduler for the Asymmetric communication and ROuting in Sensor networks architecture (AROS). The scheduler enables dynamic network reconfigurations of the AROS architecture.

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