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An efficient scheduling of AUTOSAR runnables to minimize communication cost in multi-core systems
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1384-5323
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-5297-6548
ABB Corp. Research, Vasterås, Sweden.ORCID iD: 0000-0002-3375-6766
ABB Corp. Research, Vasterås, Sweden.ORCID iD: 0000-0001-6132-7945
2014 (English)In: 2014 7th International Symposium on Telecommunications, IST 2014, 2014, 41-48 p.Conference paper, Published paper (Refereed)
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Text
Abstract [en]

The AUTOSAR consortium has developed as the worldwide standard for automotive embedded software systems. From a processor perspective, AUTOSAR was originally developed for single-core processor platforms. Recent trends have raised the desire for using multi-core processors to run AUTOSAR software. However, there are several challenges in reaching a highly efficient and predictable design of AUTOSAR-based embedded software on multi-core processors. In this paper a solution framework comprising both the mapping of runnables onto a set of tasks and the scheduling of the generated task set on a multi-core processor is suggested. The goal of the work presented in this paper is to minimize the overall inter-runnable communication cost besides meeting all corresponding timing and precedence constraints. The proposed solution framework is evaluated and compared with an exhaustive method to demonstrate the convergence to an optimal solution. Since the exhaustive method is not applicable for large size instances of the problem, the proposed framework is also compared with a well-known meta-heuristic algorithm to substantiate the capability of the frameworks to scale up. The experimental results clearly demonstrate high efficiency of the solution in terms of both communication cost and average processor utilization.

Place, publisher, year, edition, pages
2014. 41-48 p.
Keyword [en]
AUTOSAR, feedback-based search, mapping, multi-core scheduling, runnable, Simulated Annealing, SMSA, Costs, Embedded software, Embedded systems, Heuristic algorithms, Heuristic methods, Scheduling, Feed-back based, Multi core, Microprocessor chips
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:mdh:diva-31620DOI: 10.1109/ISTEL.2014.7000667Scopus ID: 2-s2.0-84931093966ISBN: 9781479953592 (print)OAI: oai:DiVA.org:mdh-31620DiVA: diva2:930185
Conference
2014 7th International Symposium on Telecommunications, IST 2014, 9 September 2014 through 11 September 2014
Available from: 2016-05-23 Created: 2016-05-23 Last updated: 2016-05-23Bibliographically approved

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Faragardi, Hamid RezaLisper, BjörnSandström, KristianNolte, Thomas

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