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Improved Priority Assignment for Real-Time Communications in On-Chip Networks
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-9736-8490
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1276-3609
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1687-930X
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-6132-7945
2015 (English)In: ACM International Conference Proceeding SeriesVolume 04-06, 2015, 171-180 p.Conference paper, Published paper (Refereed)
Abstract [en]

The Network-on-Chip is the on-chip interconnection medium of choice for modern massively parallel processors and System-on-Chip in general. Fixed-priority based preemptive scheduling using virtual-channels is a solution to support real-time communications in on-chip networks. However, the different characteristics of the Network-on-Chip compared to the single processor scheduling problem prevents the usage of known optimal algorithms (e.g. the Audsley's algorithm) to assign priorities to messages. A heuristic search algorithm based approach (called the HSA) focusing on the priority assignment for on-chip communications has been presented in the literature. The HSA is much faster than an exhaustive search based solution, with a price of missing certain schedulable cases (i.e. non-optimal). In this paper, we present two undirected-graph based priority assignment algorithms, the GESA and the GHSA. In contrast to the previous work, we can decrease the search space significantly by taking the interference dependencies of different messages on the network into account. A number of experiments are generated, in order to evaluate the proposed algorithms. The results show that the GESA can always achieve higher schedulability ratios than the HSA, but may require longer processing time. On the other hand, the GHSA has the same performance as the HSA regarding the schedulability, but can significantly improve the efficiency.

Place, publisher, year, edition, pages
2015. 171-180 p.
Keyword [en]
Network-on-ChipPriority assignmentMany-Core
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:mdh:diva-30022DOI: 10.1145/2834848.2834867ISI: 000380614800017Scopus ID: 2-s2.0-84959481086ISBN: 978-1-4503-3591-1 (print)OAI: oai:DiVA.org:mdh-30022DiVA: diva2:885624
Conference
The 23rd International Conference on Real-Time Networks and Systems RTNS'15, 4-6 Nov 2015, Lille, France
Projects
PREMISE - Predictable Multicore Systems
Available from: 2015-12-19 Created: 2015-12-18 Last updated: 2017-05-12Bibliographically approved
In thesis
1. Real-Time Communication over Wormhole-Switched On-Chip Networks
Open this publication in new window or tab >>Real-Time Communication over Wormhole-Switched On-Chip Networks
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In a modern industrial system, the requirement on computational capacity has increased dramatically, in order to support a higher number of functionalities, to process a larger amount of data or to make faster and safer run-time decisions. Instead of using a traditional single-core processor where threads can only be executed sequentially, multi-core and many-core processors are gaining more and more attentions nowadays. In a multi-core processor, software programs can be executed in parallel, which can thus boost the computational performance. Many-core processors are specialized multi-core processors with a larger number of cores which are designed to achieve a higher degree of parallel processing. An on-chip communication bus is a central intersection used for data-exchange between cores, memory and I/O in most multi-core processors. As the number of cores increases, more contention can occur on the communication bus which raises a bottleneck of the overall performance. Therefore, in order to reduce contention incurred on the communication bus, a many-core processor typically employs a Network-on-Chip (NoC) to achieve data-exchange. Real-time embedded systems have been widely utilized for decades. In addition to the correctness of functionalities, timeliness is also an important factor in such systems. Violation of specific timing requirements can result in performance degradation or even fatal problems. While executing real-time applications on many-core processors, the timeliness of a NoC, as a communication subsystem, is essential as well. Unfortunately, many real-time system designs over-provision resources to guarantee the fulfillment of timing requirements, which can lead to significant resource waste. For example, analysis of a NoC design yields that the network is already saturated (i.e. accepting more traffic can incur requirement violation), however, in reality the network actually has the capacity to admit more traffic. In this thesis, we target such resource wasting problems related to design and analysis of NoCs that are used in real-time systems. We propose a number of solutions to improve the schedulability of real-time traffic over wormhole-switched NoCs in order to further improve the resource utilization of the whole system. The solutions focus mainly on two aspects: (1) providing more accurate and efficient time analyses; (2) proposing more cost-effective scheduling methods.

Place, publisher, year, edition, pages
Västerås: Malardalen University Press, 2017
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 232
Keyword
real-time system, network-on-chips
National Category
Embedded Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-35316 (URN)978-91-7485-332-2 (ISBN)
Public defence
2017-06-20, Gamma, Västerås, 09:15 (English)
Opponent
Supervisors
Available from: 2017-05-15 Created: 2017-05-12 Last updated: 2017-07-10Bibliographically approved

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