mdh.sePublications
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Code tiling for improving the cache performance of PDE solvers
University of New South Wales, Sydney, Australia.
2003 (English)In: Proceedings of the International Conference on Parallel Processing, 2003, 615-624 p.Conference paper, Published paper (Refereed)
Abstract [en]

For SOR-like PDE solvers, loop tiling either helps little in improving data locality or hurts their performance. We present a novel compiler technique called code tiling for generating fast tiled codes for these solvers on uniprocessors with a memory hierarchy. Code tiling combines loop tiling with a new array layout transformation called data tiling in such a way that a significant amount of cache misses that would otherwise be present in tiled codes are eliminated. Compared to nine existing loop tiling algorithms, our technique delivers impressive performance speedups (faster by factors of 1.55-2.62) and smooth performance curves across a range of problem sizes on representative machine architectures. The synergy of loop tiling and data tiling allows us to find a problem-size-independent tile size that minimises a cache miss objective function independently of the problem size parameters. This "one-size-fits-all" scheme makes our approach attractive for designing fast SOR solvers without having to generate a multitude of versions specialised for different problem sizes.

Place, publisher, year, edition, pages
2003. 615-624 p.
Keyword [en]
Australia, Computer science, Data engineering, Jacobian matrices, Multidimensional systems, Partial differential equations, Processor scheduling, Tiles, Buffer storage, Cache memory, Memory architecture, Metadata, Tile, Compiler techniques, Machine architectures, Objective functions, Performance curve, Codes (symbols)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:mdh:diva-29437DOI: 10.1109/ICPP.2003.1240630Scopus ID: 2-s2.0-84944744196ISBN: 0769520170 (print)OAI: oai:DiVA.org:mdh-29437DiVA: diva2:867784
Conference
2003 International Conference on Parallel Processing, ICPP 2003, 6 October 2003 through 9 October 2003
Available from: 2015-11-06 Created: 2015-11-06 Last updated: 2015-11-06Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

Altmetric score

Total: 7 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf