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One of the main problems for underwater terrain navigation using the correlation method is the significant computing time due to the large amount of calculations. When the algorithm is used on a regular PC, the processing time is far too long for real time applications. The Swedish navy is interested in a none-revealing terrain navigation system that can perform in real time. The article describes an implementation of a navigation system into a hardware accelerator (in one FPGA supported by two SDRAMs). The use of a FPGA gives parallelism and will shorten the computing time considerable. The actual computing time has been decreased with over 100 times compared with similar PC applications. The implementation is programmed into a Virtex®-II Xilinx device and has been written in VHDL. A SDRAM controller IP-block was designed and implemented in the FPGA. Also a custom made prototype PCB board was developed in the project.