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Partitioning the Network-on-Chip to Enable Virtualization on Many-Core Processors
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1276-3609
Research and Technology Centre, Robert Bosch, India.
CISTER/INESC-TEC, ISEP, Portugal.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1687-930X
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2015 (English)In: The 6th International Real-Time Scheduling Open Problems Seminar RTSOPS'15, 2015Conference paper, Published paper (Refereed)
Abstract [en]

Technological advances have increased the transistor density, thereby ushering in multi- and more recently many-core systems, distinguished by the presence of hundreds of cores on a single chip. For such a platform, the Network-on-Chip (NoC) has emerged as a scalable and efficient interconnect fabric to realize the communication across an ever increasing number of processor cores, memories, and specialized IP blocks both on- and off-chip. In this paper, we highlighted some key problems in NoC based architectures that must be addressed before the deployment of real-time applications onto these platforms becomes possible. A paradigm shift from function centric to data and communication centric approaches is required. Combining hardware and software based flow-regulation seems to be the only way to ensure that NoCs go beyond the best-effort service and address the requirements of diverse applications.

Place, publisher, year, edition, pages
2015.
Keyword [en]
many-corereal-timeNetwork-on-Chiptraffic shaping
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:mdh:diva-28163OAI: oai:DiVA.org:mdh-28163DiVA: diva2:820570
Conference
The 6th International Real-Time Scheduling Open Problems Seminar RTSOPS'15, 7 Jul 2015, Lund, Sweden
Projects
PREMISE - Predictable Multicore Systems
Available from: 2015-06-12 Created: 2015-06-08 Last updated: 2015-06-12Bibliographically approved

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Becker, MatthiasBehnam, MorisNolte, Thomas

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CiteExportLink to record
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