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Worst Case Delay Analysis of a DRAM Memory Request for COTS Multicore Architectures
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. (Model-Based Engineering of Embedded Systems (MBEES))ORCID iD: 0000-0001-7448-3381
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1687-930X
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-7586-0409
2014 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Dynamic RAM (DRAM) is a source of memory contention and interference problems on commercial of the shelf (COTS) multicore architectures. Due to its variable access time, it can greatly influence the task's WCET and can lead to unpredictability. In this paper, we provide a worst case delay analysis for a DRAM memory request to safely bound memory contention on multicore architectures. We derive a worst-case service time for a single memory request and then combine it with the per-request memory interference that can be generated by the tasks executing on same or different cores in order to generate the delay bound.

Place, publisher, year, edition, pages
2014.
National Category
Embedded Systems Computer Systems
Research subject
Computer Science
Identifiers
URN: urn:nbn:se:mdh:diva-26540OAI: oai:DiVA.org:mdh-26540DiVA: diva2:762573
Conference
MCC14, Seventh Swedish Workshop on Multicore Computing, Lund, Nov. 27-28, 2014
Available from: 2014-11-12 Created: 2014-11-12 Last updated: 2015-01-08Bibliographically approved
In thesis
1. Hierarchical scheduling for predictable execution of real-time software components and legacy systems
Open this publication in new window or tab >>Hierarchical scheduling for predictable execution of real-time software components and legacy systems
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

This dissertation presents techniques to achieve predictable execution of coarse-grained software components and for preservation of temporal properties of components during their integration and reuse.

The dissertation presents a novel concept runnable virtual node (RVN) which interaction with the environment is bounded both by a functional and a temporal interface, and the validity of its internal temporal behaviour is preserved when integrated with other components or when reused in a new environment. The realization of RVN exploits techniques for hierarchical scheduling to achieve temporal isolation, and the principles from component-based software-engineering to achieve functional isolation. The proof-of-concept case studies executed on a micro-controller demonstrate the preserving of real-time properties within software components for predictable integration and reusability in a new environment, in both hierarchical scheduling and RVN contexts.

Further, a multi-resource server (MRS) is proposed and implemented to enable predictable execution when composing multiple real-time components on a COTS multicore platform. MRS uses resource reservation for both CPU-bandwidth and memory-bus bandwidth to bound the interferences between tasks running on the same core, as well as, between tasks running on different cores. The later could, without MRS, interfere with each other due to contention on a shared memory-bus and memory. The results indicated that MRS can be used to "encapsulate" legacy systems and to give them enough resources to fulfill their purpose. In the dissertation, the compositional schedulability analysis for MRS is also provided and an experimental study is performed to bring insight on the correlation between the server budgets.

We believe that the proposed approaches enable a faster software integration and support legacy reuse and that this work transcend the boundaries of software engineering and real-time systems.

Place, publisher, year, edition, pages
Västerås: Mälardalen University, 2014
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 169
Keyword
real-time systems, component integration and reuse, hierarchical scheduling, multicore
National Category
Embedded Systems Computer Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-26548 (URN)978-91-7485-179-3 (ISBN)
Public defence
2014-12-17, R3-151, Mälardalens högskola, Västerås, 10:00 (English)
Opponent
Supervisors
Projects
PPMSchedPROGRESS
Available from: 2014-11-13 Created: 2014-11-13 Last updated: 2014-12-03Bibliographically approved

Open Access in DiVA

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http://www.es.mdh.se/publications/3754-Worst_Case_Delay_Analysis_of_a_DRAM_Memory_Request_for_COTS_Multicore_Architectures

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