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Response time analysis of multi-hop HaRTES Ethernet Switch networks
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0003-3469-1834
DETI/IT, University of Aveiro, Aveiro, Portugal .
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1687-930X
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Technische Universiteit Eindhoven (TU/e), Netherlands .ORCID iD: 0000-0001-6234-5117
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2014 (English)In: IEEE Int. Workshop Factory Commun. Syst. Proc. WFCS, 2014Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we focus on micro-segmented switched-Ethernet networks with HaRTES switches. HaRTES switches provide synchronous and asynchronous real-time traffic scheduling, dynamic Quality-of-Service adaptation and transparent integration of real-time and non-real-time nodes. Herein we investigate the challenges of connecting multiple HaRTES switches in order to build multi-hop communication and we propose a method, named Distributed Global Scheduling, to handle the traffic forwarding in such an architecture while preserving the unique properties of the single HaRTES switch case. Moreover, we develop a response time analysis for the method. We also evaluate the level of pessimism embodied in the anal-ysis. Finally, we show the applicability of the proposed method in an industrial setting by applying it in an automotive case study.

Place, publisher, year, edition, pages
2014.
Series
IEEE International Workshop on Factory Communication Systems - Proceedings, WFCS
National Category
Engineering and Technology Computer and Information Science
Identifiers
URN: urn:nbn:se:mdh:diva-25722DOI: 10.1109/WFCS.2014.6837579ISI: 000356767300004Scopus ID: 2-s2.0-84903977537ISBN: 9781479932351 (print)OAI: oai:DiVA.org:mdh-25722DiVA: diva2:735473
Conference
10th IEEE Workshop on Factory Communication Systems, WFCS 2014, 5 May 2014 through 7 May 2014, Toulouse
Available from: 2014-07-28 Created: 2014-07-25 Last updated: 2015-07-16Bibliographically approved
In thesis
1. Multi-Hop Real-Time Communication over Switched Ethernet Technology
Open this publication in new window or tab >>Multi-Hop Real-Time Communication over Switched Ethernet Technology
2014 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Switched Ethernet technology has been introduced to be exploited in real-time communication systems due to its features such as its high throughput and wide availability, hence being a cost-effective solution. Many real-time switched Ethernet protocols have been developed, preserving the profits of traditional Ethernet technology, to overcome the limitations imposed by using commercially available (COTS) switches. These limitations mainly originate from the non-deterministic behavior of the Ethernet switches inherent in the use of FIFO queues and a limited number of priority levels.

 

In our research we focus on two particular real-time communication technologies, one based on COTS Ethernet switches named the FTT-SE architecture and the other using a modified Ethernet switch called the HaRTES architecture. Both architectures are based on a master-slave technique supporting different and temporally isolated traffic types including real-time periodic, real-time sporadic and non-real-time traffic. Also, they provide mechanisms implementing adaptivity as a response to the requirements imposed by dynamic real-time applications. Nevertheless, the two mentioned architectures were originally developed for a simple network consisting of a single switch, and they were lacking support for multi-hop communication. In industrial applications, multi-hop communication is essential as the networks comprise a high number of nodes, that is far beyond the capability of a single switch.

 

In this thesis, we study the challenges of building multi-hop communication using the FTT-SE and the HaRTES architectures. We propose different architectures to provide multi-hop communication while preserving the key characteristics of the single-switch architecture such as timeliness guarantee, resource efficiency, adaptivity and dynamicity. We develop a response time analysis for each proposed architecture and we compare them to assess their corresponding benefits and limitations. Further, we develop a simulation tool to evaluate the solutions.

Place, publisher, year, edition, pages
Västerås: Mälardalen University, 2014
Series
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 184
National Category
Embedded Systems Communication Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-26121 (URN)978-91-7485-168-7 (ISBN)
Presentation
2014-11-18, Delta, Mälardalens högskola, Västerås, 13:30 (English)
Opponent
Supervisors
Available from: 2014-10-20 Created: 2014-10-17 Last updated: 2014-11-12Bibliographically approved

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