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Reduced Buffering Solution for Multi-Hop HaRTES Switched Ethernet Networks
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0003-3469-1834
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1687-930X
University of Aveiro, Portugal.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0001-6234-5117
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2014 (English)In: The 20th IEEE International Conference on embedded and Real-Time Computing Systems and Applications RTCSA'14, 2014, Article number 6910504- p.Conference paper, Published paper (Refereed)
Abstract [en]

In the context of switched Ethernet networks, multi-hop communication is essential as the networks in industrial applications comprise a high amount of nodes, that is far beyond the capability of a single switch. In this paper, we focus on multi-hop communication using HaRTES switches. The HaRTES switch is a modified Ethernet switch that provides real-time traffic scheduling, dynamic Quality-of-Service and temporal isolation between real-time and non-real-time traffic. Herein, we propose a method, called Reduced Buffering Scheme, to conduct the traffic through multiple HaRTES switches in a multi-hop HaRTES architecture. In order to enable the new scheduling method we propose to modify the HaRTES switch structure. Moreover, we develop a response time analysis for the new method. We also compare the proposed method with a method previously proposed, called Distributed Global Scheduling, based on their traffic response times. We show that, the new method forwards all types of traffic including the highest, the medium and the lowest priority, faster than the previous method in most of the cases. Furthermore, we show that the new method performs even better for larger networks compared with the previous one.

Place, publisher, year, edition, pages
2014. Article number 6910504- p.
Keyword [en]
Switched Ethernet, Real-Time Communication, Multi-hop communication
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-25189DOI: 10.1109/RTCSA.2014.6910504ISI: 000352610400008Scopus ID: 2-s2.0-84908626169ISBN: 978-1479939534 (print)OAI: oai:DiVA.org:mdh-25189DiVA: diva2:722105
Conference
20th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2014; Chongqing; China; 20 August 2014 through 22 August 2014
Projects
PRESS - Predictable Embedded Software Systems
Available from: 2014-06-05 Created: 2014-06-05 Last updated: 2015-12-23Bibliographically approved
In thesis
1. Multi-Hop Real-Time Communication over Switched Ethernet Technology
Open this publication in new window or tab >>Multi-Hop Real-Time Communication over Switched Ethernet Technology
2014 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Switched Ethernet technology has been introduced to be exploited in real-time communication systems due to its features such as its high throughput and wide availability, hence being a cost-effective solution. Many real-time switched Ethernet protocols have been developed, preserving the profits of traditional Ethernet technology, to overcome the limitations imposed by using commercially available (COTS) switches. These limitations mainly originate from the non-deterministic behavior of the Ethernet switches inherent in the use of FIFO queues and a limited number of priority levels.

 

In our research we focus on two particular real-time communication technologies, one based on COTS Ethernet switches named the FTT-SE architecture and the other using a modified Ethernet switch called the HaRTES architecture. Both architectures are based on a master-slave technique supporting different and temporally isolated traffic types including real-time periodic, real-time sporadic and non-real-time traffic. Also, they provide mechanisms implementing adaptivity as a response to the requirements imposed by dynamic real-time applications. Nevertheless, the two mentioned architectures were originally developed for a simple network consisting of a single switch, and they were lacking support for multi-hop communication. In industrial applications, multi-hop communication is essential as the networks comprise a high number of nodes, that is far beyond the capability of a single switch.

 

In this thesis, we study the challenges of building multi-hop communication using the FTT-SE and the HaRTES architectures. We propose different architectures to provide multi-hop communication while preserving the key characteristics of the single-switch architecture such as timeliness guarantee, resource efficiency, adaptivity and dynamicity. We develop a response time analysis for each proposed architecture and we compare them to assess their corresponding benefits and limitations. Further, we develop a simulation tool to evaluate the solutions.

Place, publisher, year, edition, pages
Västerås: Mälardalen University, 2014
Series
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 184
National Category
Embedded Systems Communication Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-26121 (URN)978-91-7485-168-7 (ISBN)
Presentation
2014-11-18, Delta, Mälardalens högskola, Västerås, 13:30 (English)
Opponent
Supervisors
Available from: 2014-10-20 Created: 2014-10-17 Last updated: 2014-11-12Bibliographically approved

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