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Supporting Multi-Hop Communications with HaRTES Ethernet Switches
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. (IS (Embedded Systems))ORCID iD: 0000-0003-3469-1834
University of Aveiro, Portugal.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. (IS (Embedded Systems))ORCID iD: 0000-0002-1687-930X
University of Porto, Portugal.
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2013 (English)Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we identify the challenges of multi-hop communication when using a micro-segmented switched-Ethernet protocol with enhanced HaRTES switches. The HaRTES architecture has been explored in the scope of single-switch topology, and provides dynamic virtual channels that can be composed hierarchically and provide bounded latency together with temporal isolation. Herein we propose two different solutions regarding the traffic forwarding in multi-switch architectures, while maintaining the unique properties of the single HaRTES switch case. In the first approach, the traffic is buffered and scheduled sequentially in each hop. In the second solution the traffic is scheduled once and forwarded immediately through multiple switches without buffering. In this paper we present a brief comparison of both approaches and we report on the on-going work towards effective support to real-time communications in dynamic and complex Cyber-Physical Systems.

Place, publisher, year, edition, pages
2013.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-23312OAI: oai:DiVA.org:mdh-23312DiVA: diva2:679078
Conference
IEEE Real-Time Systems Symposium Work-in-Progress (WiP) session, RTSS 2013, December 3-6, Vancouver, Canada
Projects
PRESS - Predictable Embedded Software Systems
Available from: 2013-12-13 Created: 2013-12-10 Last updated: 2016-11-01Bibliographically approved

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