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Performance Analysis of Master-Slave Multi-Hop Switched Ethernet Networks
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. (IS (Embedded Systems))ORCID iD: 0000-0003-3469-1834
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. (IS (Embedded Systems))ORCID iD: 0000-0002-1687-930X
University of Porto, Portugal.ORCID iD: 0000-0002-9544-3028
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. (IS (Embedded Systems))ORCID iD: 0000-0001-6132-7945
2013 (English)In: Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, SIES 2013, 2013, p. 280-289Conference paper, Published paper (Refereed)
Abstract [en]

There is an increasing trend towards using switched Ethernet in real-time distributed systems due to features like absence of collisions and high throughput. Nevertheless, a few problems persist, in particular related to priority inversion and limited length in queues. In this paper we focus on a protocol which uses a master-slave technique over standard switched Ethernet in order to overcome such problems, namely FTT-SE protocol. We present an improved response time analysis for such a network and we compare, analytically and with simulations, the results achieved with Network Calculus on a worst-case scenario. We show that our proposed response time analysis gives tighter bounds compared to Network Calculus. Moreover, we compare the performance of different solutions to scale the FTT-SE protocol with respect to the bandwidth utilization. Finally, we propose a new architecture to improve the average performance of master-slave switched Ethernet networks.

Place, publisher, year, edition, pages
2013. p. 280-289
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-21348DOI: 10.1109/SIES.2013.6601501Scopus ID: 2-s2.0-84885416264ISBN: 9781479906581 (print)OAI: oai:DiVA.org:mdh-21348DiVA, id: diva2:649544
Conference
8th IEEE International Symposium on Industrial Embedded Systems (SIES13), Porto, Portugal, June 19-21, 2013
Projects
PRESS - Predictable Embedded Software Systems
Available from: 2013-09-18 Created: 2013-09-11 Last updated: 2016-11-01Bibliographically approved
In thesis
1. Multi-Hop Real-Time Communication over Switched Ethernet Technology
Open this publication in new window or tab >>Multi-Hop Real-Time Communication over Switched Ethernet Technology
2014 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Switched Ethernet technology has been introduced to be exploited in real-time communication systems due to its features such as its high throughput and wide availability, hence being a cost-effective solution. Many real-time switched Ethernet protocols have been developed, preserving the profits of traditional Ethernet technology, to overcome the limitations imposed by using commercially available (COTS) switches. These limitations mainly originate from the non-deterministic behavior of the Ethernet switches inherent in the use of FIFO queues and a limited number of priority levels.

 

In our research we focus on two particular real-time communication technologies, one based on COTS Ethernet switches named the FTT-SE architecture and the other using a modified Ethernet switch called the HaRTES architecture. Both architectures are based on a master-slave technique supporting different and temporally isolated traffic types including real-time periodic, real-time sporadic and non-real-time traffic. Also, they provide mechanisms implementing adaptivity as a response to the requirements imposed by dynamic real-time applications. Nevertheless, the two mentioned architectures were originally developed for a simple network consisting of a single switch, and they were lacking support for multi-hop communication. In industrial applications, multi-hop communication is essential as the networks comprise a high number of nodes, that is far beyond the capability of a single switch.

 

In this thesis, we study the challenges of building multi-hop communication using the FTT-SE and the HaRTES architectures. We propose different architectures to provide multi-hop communication while preserving the key characteristics of the single-switch architecture such as timeliness guarantee, resource efficiency, adaptivity and dynamicity. We develop a response time analysis for each proposed architecture and we compare them to assess their corresponding benefits and limitations. Further, we develop a simulation tool to evaluate the solutions.

Place, publisher, year, edition, pages
Västerås: Mälardalen University, 2014
Series
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 184
National Category
Embedded Systems Communication Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-26121 (URN)978-91-7485-168-7 (ISBN)
Presentation
2014-11-18, Delta, Mälardalens högskola, Västerås, 13:30 (English)
Opponent
Supervisors
Available from: 2014-10-20 Created: 2014-10-17 Last updated: 2014-11-12Bibliographically approved

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Ashjaei, MohammadBehnam, MorisAlmeida, LuisNolte, Thomas

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