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Validating EAST-ADL Timing Constraints using UPPAAL
Mälardalen University, School of Innovation, Design and Engineering. (IS (Embedded Systems))
2013 (English)In: 39th Euromicro Conference on Software Engineering and Advanced Applications (SEAA), 2013Conference paper, Published paper (Refereed)
Abstract [en]

Systematic and formal development approaches for safety- and mission critical systems are of increasing importance. These systems are often implemented as periodically triggered control systems, to ensure deterministic and analyzable timing behavior. However, integrating timing ‘constraints’ in the development process remains a challenging task. For instance, these constraints itself should be formally verified as consistent and feasible with respect to the system design. In this paper, we present a timed automata based validation approach for EAST-ADL timing constraints for periodic control systems. The constraints are specified using CCSL – the Clock Constraint Specification Language,and transformed into timed automata, to enable formal verification with UPPAAL model-checker. The resulting timed automata specification can be simulated and verified for the formal validation of the timing constraints. Further, the transformed specification model can be easily integrated with the actual system design, thus extending verification aspects. The proposed approach is demonstrated using the timing constraints for an Anti-lock Braking System (ABS) example.

Place, publisher, year, edition, pages
2013.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-21400DOI: 10.1109/SEAA.2013.46Scopus ID: 2-s2.0-84889061215OAI: oai:DiVA.org:mdh-21400DiVA: diva2:648461
Conference
39th Euromicro Conference on Software Engineering and Advanced Applications (SEAA 2013) Santander, Spain September 4-6, 2013
Projects
ARROWS - Design Techniques for Adaptive Embedded Systems
Available from: 2013-09-16 Created: 2013-09-11 Last updated: 2016-06-02Bibliographically approved
In thesis
1. Model Based Development of Embedded Systems using Logical Clock Constraints and Timed Automata
Open this publication in new window or tab >>Model Based Development of Embedded Systems using Logical Clock Constraints and Timed Automata
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In modern times, human life is intrinsically depending on real-time embedded systems (RTES) with increasingly safety-critical and mission-critical features, for instance, in domains such as automotive and avionics. These systems are characterized by stringent functional requirements and require predictable timing behavior. However, the complexity of RTES has been ever increasing requiring systematic development methods. To address these concerns, model-based frameworks and component-based design methodologies have emerged as a feasible solution. Further, system artifacts such as requirements/specifications, architectural designs as well as behavioral models like statemachine views are integrated within the development process. However, several challenges remain to be addressed, out of which two are especially important: expressiveness, to represent the real-time and causality behavior, and analyzability, to support verification of functional and timing behavior.

As the main research contribution, this thesis presents design and verification techniques for model-based development of RTES, addressing expressiveness and analyzability for architectural and behavioral models. To begin with, we have proposed a systematic design process to support component-based development. Next, we have provided a real-time semantic basis, in order to support expressiveness and verification for structural and behavioral models. This is achieved by defining an intuitive formal semantics for real-time component models, using ProCom, a component model developed at our research centre, and also using the CCSL (Clock Constraint Specification Language), an expressive language for specification of timed causality behavior. This paves the way for formal verification of both architectural and behavioral models, using model checking, as we show in this work, by transforming the models into timed automata and performing verification using UPPAAL, a model checking tool based on timed automata. Finally, the research contributions are validated using representative examples of RTES as well as an industrial case-study.

Place, publisher, year, edition, pages
Västerås: Mälardalen University, 2013
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 146
Keyword
Embedded Systems, Model-based development, Model-Checking, Architectural Modeling, CCSL, Timed Automata
National Category
Embedded Systems
Identifiers
urn:nbn:se:mdh:diva-22328 (URN)978-91-7485-123-6 (ISBN)
Public defence
2013-12-09, Kappa, Mälardalen University, Västerås, 13:15 (English)
Opponent
Supervisors
Projects
ARROWS
Funder
Swedish Research Council, 2270 430 16243
Available from: 2013-11-01 Created: 2013-11-01 Last updated: 2013-11-18Bibliographically approved

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