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The Impact of Intra-core and Inter-core Task Communication on Architectural Analysis of Multicore Embedded Systems
Mälardalen University, School of Innovation, Design and Engineering. (IS (Embedded Systems))ORCID iD: 0000-0002-8486-5110
Mälardalen University, School of Innovation, Design and Engineering. (IS (Embedded Systems))ORCID iD: 0000-0002-8461-0230
2013 (English)Conference paper, Published paper (Refereed)
Abstract [en]

In order to get accurate performance predictions, design-time architectural analysis of multicore embedded systems has to consider communication overhead. When communicating tasks execute on the same core, the communication typically happens through the local cache. On the other hand, when they run on separate cores, the communication has to go through the shared memory. As the shared memory has a significantly larger latency than the local cache, we expect a significant difference between intra-core and inter-core task communication. In this paper, we present a series of experiments we ran to identify the size of this difference, and discuss its impact on architectural analysis of multicore embedded systems. In particular, we show that the impact of the difference is much lower than anticipated.

Place, publisher, year, edition, pages
2013. p. 402-407
Keywords [en]
software architecture, model-based analysis, multicore embedded systems, task communication, measurement, cache
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-21418ISBN: 978-1-61208-304-9 (print)OAI: oai:DiVA.org:mdh-21418DiVA, id: diva2:647591
Conference
The Eighth International Conference on Software Engineering Advances, ICSEA 2013, October 27 - November 1, 2013 - Venice, Italy
Projects
CONTESSE - Contract-Based Components for Embedded SoftwareRALF3 - Software for Embedded High Performance ArchitecturesAvailable from: 2013-09-11 Created: 2013-09-11 Last updated: 2014-02-06Bibliographically approved

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Feljan, JurajCarlson, Jan

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