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Analysis support for TADL2 timing constraints on EAST-ADL models
AOSTE Team, UNS-I3S-INRIA, Sophia-Antipolis, France .
Mälardalen University, School of Innovation, Design and Engineering.
AOSTE Team, UNS-I3S-INRIA, Sophia-Antipolis, France .
AOSTE Team, UNS-I3S-INRIA, Sophia-Antipolis, France .
2013 (English)In: Lecture Notes in Computer Science, vol. 7957, Springer, 2013, 89-105 p.Chapter in book (Refereed)
Abstract [en]

It is critical to analyze characteristics of real-time embedded systems, such as timing behavior, early in the development. In the automotive domain, EAST-ADL is a concrete example of the model-based approach for the architectural modeling of real-time systems. The Timing Augmented Description Language v2 (TADL2) allows for the specification of timing constraints on top of EAST-ADL models. In this paper we propose a formal validation & verification methodology for timing behaviors given with TADL2. The formal semantics of the timing constraints is given as a mapping to the Clock Constraint Specification Language (CCSL), a formal language that implements the MARTE Time Model. Based on such a mapping, the validation is carried out by the simulation of TADL2 specifications. The simulation allows for a rapid prototyping of TADL2 specifications. The verification is performed based on a TADL2 mapping to timed automata modeling using the Uppaal model-checker. The whole process is illustrated on a Brake-By-Wire application.

Place, publisher, year, edition, pages
Springer, 2013. 89-105 p.
Series
Lecture Notes in Computer Science, ISSN 0302-9743 ; 7957
Series
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 7957
Keyword [en]
Architectural modeling, Automotive domains, Clock constraints, Description languages, Model based approach, Real-time embedded systems, Timing constraints, Verification methodology, Automata theory, Formal languages, Model checking, Rapid prototyping, Real time systems, Software architecture, Specification languages, Specifications, Mapping
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-20823DOI: 10.1007/978-3-642-39031-9_8Scopus ID: 2-s2.0-84879852991ISBN: 9783642390302 (print)OAI: oai:DiVA.org:mdh-20823DiVA: diva2:638803
Conference
7th European Conference on Software Architecture, ECSA 2013, 1 July 2013 through 5 July 2013, Montpellier
Note

7th European Conference on Software Architecture, ECSA 2013; Montpellier; France; 1 July 2013 through 5 July 2013

Available from: 2013-08-02 Created: 2013-08-02 Last updated: 2016-05-17Bibliographically approved
In thesis
1. Model Based Development of Embedded Systems using Logical Clock Constraints and Timed Automata
Open this publication in new window or tab >>Model Based Development of Embedded Systems using Logical Clock Constraints and Timed Automata
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In modern times, human life is intrinsically depending on real-time embedded systems (RTES) with increasingly safety-critical and mission-critical features, for instance, in domains such as automotive and avionics. These systems are characterized by stringent functional requirements and require predictable timing behavior. However, the complexity of RTES has been ever increasing requiring systematic development methods. To address these concerns, model-based frameworks and component-based design methodologies have emerged as a feasible solution. Further, system artifacts such as requirements/specifications, architectural designs as well as behavioral models like statemachine views are integrated within the development process. However, several challenges remain to be addressed, out of which two are especially important: expressiveness, to represent the real-time and causality behavior, and analyzability, to support verification of functional and timing behavior.

As the main research contribution, this thesis presents design and verification techniques for model-based development of RTES, addressing expressiveness and analyzability for architectural and behavioral models. To begin with, we have proposed a systematic design process to support component-based development. Next, we have provided a real-time semantic basis, in order to support expressiveness and verification for structural and behavioral models. This is achieved by defining an intuitive formal semantics for real-time component models, using ProCom, a component model developed at our research centre, and also using the CCSL (Clock Constraint Specification Language), an expressive language for specification of timed causality behavior. This paves the way for formal verification of both architectural and behavioral models, using model checking, as we show in this work, by transforming the models into timed automata and performing verification using UPPAAL, a model checking tool based on timed automata. Finally, the research contributions are validated using representative examples of RTES as well as an industrial case-study.

Place, publisher, year, edition, pages
Västerås: Mälardalen University, 2013
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 146
Keyword
Embedded Systems, Model-based development, Model-Checking, Architectural Modeling, CCSL, Timed Automata
National Category
Embedded Systems
Identifiers
urn:nbn:se:mdh:diva-22328 (URN)978-91-7485-123-6 (ISBN)
Public defence
2013-12-09, Kappa, Mälardalen University, Västerås, 13:15 (English)
Opponent
Supervisors
Projects
ARROWS
Funder
Swedish Research Council, 2270 430 16243
Available from: 2013-11-01 Created: 2013-11-01 Last updated: 2013-11-18Bibliographically approved

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Citation style
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