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Practical experiences of applying source-level WCET flow analysis to industrial code
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. (IS)ORCID iD: 0000-0001-5297-6548
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. (IS)
Vienna University of Technology.
Vienna University of Technology.
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2013 (English)In: International Journal on Software Tools for Technology Transfer (STTT), ISSN 1385-4879, E-ISSN 1571-8115, Vol. 15, no 1, 53-63 p.Article in journal (Refereed) Published
Abstract [en]

Code-level timing analysis, such as worst-case execution time (WCET) analysis, usually takes place at the binary level. However, many program properties that are important for the analysis, such as constraints on possible program flows, are easier to derive at the source code level since this code contains much more information. Therefore, various source-level analyses can provide valuable support for timing analysis. However, source-level analysis is not always smoothly applicable in industrial settings. In this paper, we report on the experiences of applying source-level analysis to industrial code in the ALL-TIMES project: the promises, the pitfalls, and the workarounds that were developed. We also discuss various approaches to how the difficulties that were encountered can be tackled.

Place, publisher, year, edition, pages
2013. Vol. 15, no 1, 53-63 p.
Keyword [en]
Embedded software, Source-level analysis, Static analysis, WCET analysis
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-18231DOI: 10.1007/s10009-012-0255-9Scopus ID: 2-s2.0-84872976866OAI: oai:DiVA.org:mdh-18231DiVA: diva2:605766
Projects
ALL-TIMESWorst-Case Execution Time Analysis of Parallel Systems
Available from: 2013-02-15 Created: 2013-02-15 Last updated: 2015-11-04Bibliographically approved

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Lisper, BjörnErmedahl, Andreas
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Citation style
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Language
  • de-DE
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  • nn-NB
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Output format
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