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Probabilistic Preemption Control using Frequency Scaling for Sporadic Real-time Tasks
Mälardalen University, School of Innovation, Design and Engineering. (IS)ORCID iD: 0000-0002-6355-3564
Mälardalen University, School of Innovation, Design and Engineering. (IS)ORCID iD: 0000-0003-4157-3537
Mälardalen University, School of Innovation, Design and Engineering. (IS)ORCID iD: 0000-0001-5269-3900
2012 (English)In: 7th IEEE International Symposium on IndustrialEmbedded Systems (SIES): Conference Proceedings, IEEE Computer Society, 2012, p. 158-165Conference paper, Published paper (Refereed)
Abstract [en]

Preemption related costs are major sources of unpredictability in the task execution times in a real-time system. We examine the possibility of using CPU frequency scaling to control the preemption behavior of real-time sporadic tasks scheduled using a preemptive Fixed Priority Scheduling (FPS) policy. Our combined offline-online method provides probabilistic preemption control guarantees by making use of the release time probabilities of the sporadic tasks. The offline phase derives the probability related deviation from the minimum inter-arrival time of tasks. The online algorithm uses this information to calculate appropriate CPU frequencies that guarantees non-preemptive task executions while preserving the overall system schedulability. The online algorithm has a linear complexity and does not lead to significant implementation overheads. Our evaluations demonstrate the effectiveness of the method as well as the possibility of energy-preemption trade offs. Even though we have considered FPS, our method can easily be extended to dynamic priority scheduling schemes

Place, publisher, year, edition, pages
IEEE Computer Society, 2012. p. 158-165
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-16075DOI: 10.1109/SIES.2012.6356581Scopus ID: 2-s2.0-84871567582ISBN: 978-1-4673-2683-4 (print)OAI: oai:DiVA.org:mdh-16075DiVA, id: diva2:563682
Conference
The 7th IEEE International Symposium on Industrial Embedded Systems, Karlsruhe, Germany, June 20-22, 2012
Available from: 2012-10-31 Created: 2012-10-31 Last updated: 2013-12-03Bibliographically approved
In thesis
1. Resource Augmentation for Performance Guarantees in Embedded Real-time Systems
Open this publication in new window or tab >>Resource Augmentation for Performance Guarantees in Embedded Real-time Systems
2012 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Real-time scheduling policies have been widely studied, with many known schedulability and feasibility analysis techniques for different task models, that have advanced the state-of-the-art. Most of these techniques are typically derived under the assumption of negligible runtime overheads which may not be realistic for modern embedded real-time systems, and hence potentially compromises the guarantees on their correct behaviors. This calls for methods to reason about the functioning of the system under the presence of such overheads as well as to predictably control them. Controlling these overheads may place additional performance demands, consequently requiring more resources such as faster processors. At the same time, the need for energy efficiency in these class of systems further complicates the problem and necessitates a holistic approach.

In this thesis, we apply resource augmentation, viz., processor speed-up, to guarantee desired real-time properties even under the presence of runtime overheads. We specifically consider preemptions and faults that, at runtime, manifest as overheads in the system in various ways. Our aim is to provide specified non-preemption and fault tolerance feasibility guarantees in a real-time system. We first propose offline and online methods, that uses CPU frequency scaling, to control the number of preemptions in periodic and sporadic task systems, under a preemptive Fixed Priority Scheduling (FPS) policy. Furthermore, we derive the resource augmentation bound, specifically the upper-bound on the lowest processor speed, that guarantees the feasibility of a specified non-preemption behavior for any real-time task. We show that, for any task Ti , the resource augmentation bound that guarantees a non- reemptive execution for a specified duration Li , is given by 4Li/Dmin, where Dmin  is the shortest deadline in the task set. Consequently, we show that the upper-bound on the lowest processor speed that guarantees the feasibility of a non-preemptive schedule for the task set is 4Cmax/Dmin, where Cmax  is the largest execution time in the task set. We then propose a method to guarantee specified upper-bounds on the preemption related overheads in the schedule. We first translate the requirements of meeting specified upper-bounds on the preemption related overheads to a set of non-preemption requirements for the task set. The resource augmentation bound in conjunction with a sensitivity analysis is used to calculate the optimal processor speed that guarantees the derived non-preemption requirements, achieving the specified bounds on the preemption related costs. Finally, we derive the resource augmentation bound that guarantees the fault tolerance feasibility of a set of real-time tasks under an error burst of known length. We show that if the error burst length is no longer than half the shortest deadline in the task set, the resource augmentation bound that guarantees fault tolerance feasibility is 6. 

Our contribution bounds the extra resources, specifically the required processor speed-up, that provides specified non-preemption and fault tolerance feasibility guarantees in a real-time system. It allows us to quantify the 'goodness' of non-preemptive scheduling, referred to as its sub-optimality, as compared to an optimal uni-processor scheduling algorithm, in terms of the required processor speed-up that guarantees a non-preemptive schedule for any uni-processor feasible task set. We intend to extend this work to provide non-preemption and fault tolerance feasibility guarantees in multi-processor systems.

Place, publisher, year, edition, pages
Västerås: Malardalen University, 2012
Series
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 160
National Category
Computer and Information Sciences
Identifiers
urn:nbn:se:mdh:diva-16092 (URN)978-91-7485-086-4 (ISBN)
Presentation
2012-11-30, Kappa, Mälardalens högskola, Västerås, 09:15 (English)
Opponent
Supervisors
Available from: 2012-11-02 Created: 2012-11-01 Last updated: 2018-01-12Bibliographically approved

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Thekkilakattil, AbhilashDobrin, RaduPunnekkat, Sasikumar

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