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Power and Area Efficient Design of Network-on-Chip Router through Utilization of Idle Buffers
University of Turku.
Mälardalen University, School of Innovation, Design and Engineering.ORCID iD: 0000-0003-1996-1234
Turku Centre for Computer Science.
2010 (English)In: / [ed] IEEE, 2010, 131-138 p.Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) is the interconnection platform that answers the requirements of the modern on-Chip design. Small optimizations in NoC router architecture can show a significant improvement in the overall performance of NoC based systems. Power consumption, area overhead and the entire NoC performance is influenced by the router buffers. Resource sharing for on-chip network is critical to reduce the chip area and power consumption. Virtual channel buffer sharing by other router ports has been proposed to enhance the performance of on-chip communication. We approach the router architecture optimization by utilizing the idle buffers instead of increasing the number and size of buffers for desired throughput.

Place, publisher, year, edition, pages
2010. 131-138 p.
Identifiers
URN: urn:nbn:se:mdh:diva-13132DOI: 10.1109/ECBS.2010.21OAI: oai:DiVA.org:mdh-13132DiVA: diva2:448001
Conference
The 17th Annual IEEE International Conference on the Engineering of Computer Based Systems (ECBS)
Available from: 2011-10-13 Created: 2011-10-13 Last updated: 2013-12-03Bibliographically approved

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
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Language
  • de-DE
  • en-GB
  • en-US
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  • nn-NO
  • nn-NB
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Output format
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