https://www.mdu.se/

Current approaches to feature detection and matching

in images strive to increase the repeatability of the detector

and minimize the degree of outliers in the matching.

In this paper we present a conflicting approach; we suggest

that a lower performance feature detector can produce

a result more than adequate for robot navigation irrespectively

of the amount of outliers. By using an FPGA

together with two cameras we can remove the need for

descriptors by performing what we call spurious matching

and the use of 3D landmarks. The approach bypasses

the problem of outliers and reduces the time consuming

task of data association, which slows many matching algorithms.

This paper proposes a limited implementation of areabasedstereo matching for minimal resource utilization. It shows that it is possible to achieve an acceptable disparity map without the use of expensive resources. The matching accuracy for the single-row SAD can even outperform that of its full-row counterpart. Additionally, it excels in terms of frame rate and resource utilization, and is highly suitable for real-time stereo-vision systems.

This paper presents a set of approaches for increasing the accuracy of basic area-based stereo matching methods. It is targeting real-time FPGA systems for dense disparity map estimation. The methods are focused on low resource usage and maximized improvement per cost unit to enable the inclusion of an autonomous system in an FPGA. The approach performs on par with other area-matching implementations, but at substantially lower resource usage. Additionally, the solution removes the requirement for external memory for reconfigurable hardware together with the limitation in image size accompanying standard methods. As a fully piped complete on-chip solution, it is highly suitable for real-time stereo-vision systems, with a frame rate over 100 fps for Megapixel images.