UPPAAL PORT is a new tool for component-based design and analysis
of embedded systems. It operates on the hierarchically structured continuous time component modeling language SaveCCM and provides efficient model-checking
by using partial-order reduction techniques that exploits the structure and the component behavior of the model. UPPAAL PORT is implemented as an extension of the verification engine in the UPPAAL tool. The tool can be used as back-end in to the Eclipse based SaveCCM integrated development environment, which
supports user friendly editing, simulation, and verification of models.
6th International Symposium on Automated Technology for Verification and Analysis, ATVA 2008; Seoul; South Korea; 20 October 2008 through 23 October 2008