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Proportional Cache-fair Scheduling for Multi-core Systems
Mälardalen University, School of Innovation, Design and Engineering.
Mälardalen University, School of Innovation, Design and Engineering.ORCID iD: 0000-0002-5274-7339
2008 (English)In: Proceedings Work-In-Progress Session of the 20th Euromicro Conference on Real-Time Systems, 2008, p. 48-51Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present a cache-aware real-time scheduling algorithm for multi-core platforms. It uses the standard timing constrains of the tasks together with the hardware counter statistics to yield unique task priorities. Scheduling according to timing constraints criterion enforces timely completion of the tasks while the cache-fair thread scheduling ensures that tasks to which shared caches are unequally allocated are compensated by assigning more or less processor time.

Place, publisher, year, edition, pages
2008. p. 48-51
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:mdh:diva-7196OAI: oai:DiVA.org:mdh-7196DiVA, id: diva2:237206
Conference
The 20th Euromicro Conference on Real-Time Systems, July 2-4, 2008, Prague, Czech Republic
Available from: 2009-09-25 Created: 2009-09-25 Last updated: 2016-01-08Bibliographically approved

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https://www.ideals.illinois.edu/bitstream/handle/2142/11461/Proceedings%20Work-In-Progress%20Session%20of%20the%2020th%20Euromicro%20Conference%20on%20Real-Time%20Systems.pdf?sequence=2

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Isovic, Damir

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CiteExportLink to record
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Citation style
  • apa
  • ieee
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