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Data cache locking for tight timing calculations
Mälardalen University, Department of Computer Science and Electronics.
Mälardalen University, Department of Computer Science and Electronics.ORCID iD: 0000-0001-5297-6548
Mälardalen University, Department of Computer Science and Electronics.
2008 (English)In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 7, no 1Article in journal (Refereed) Published
Abstract [en]

Caches have become increasingly important with the widening gap between main memory and processor speeds. Small and fast cache memories are designed to bridge this discrepancy. However, they are only effective when programs exhibit sufficient data locality. In addition, caches are a source of unpredictability, resulting in programs sometimes behaving in a different way than expected. Detailed information about the number of cache misses and their causes allows us to predict cache behavior and to detect bottlenecks. Small modifications in the source code may change memory patterns, thereby altering the cache behavior. Code transformations, which take the cache behavior into account, might result in a high cache performance improvement. However, cache memory behavior is very hard to predict, thus making the task of optimizing and timing cache behavior very difficult. This article proposes and evaluates a new compiler framework that times cache behavior for multitasking systems. Our method explores the use of cache partitioning and dynamic cache locking to provide worst-case performance estimates in a safe and tight way for multitasking systems. We use cache partitioning, which divides the cache among tasks to eliminate intertask cache interferences. We combine static cache analysis and cache-locking mechanisms to ensure that all intratask conflicts, and consequently, memory access times, are exactly predictable. The results of our experiments demonstrate the capability of our framework to describe cache behavior at compile time. We compare our timing approach with a system equipped with a nonpartitioned, but statically, locked data cache. Our method outperforms static cache locking for all analyzed task sets under various cache architectures, demonstrating that our fully predictable scheme does not compromise the performance of the transformed programs.

Place, publisher, year, edition, pages
2008. Vol. 7, no 1
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-7107DOI: 10.1145/1324969.1324973ISI: 000256880700004Scopus ID: 2-s2.0-38349171771OAI: oai:DiVA.org:mdh-7107DiVA, id: diva2:237117
Available from: 2009-09-25 Created: 2009-09-25 Last updated: 2019-06-26Bibliographically approved

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Lisper, Björn

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