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Maximizing the Fault Tolerance Capability of Fixed Priority Schedules
Mälardalen University, Department of Innovation, Design and Product Development.ORCID iD: 0000-0003-4157-3537
Mälardalen University, Department of Innovation, Design and Product Development.ORCID iD: 0000-0001-5053-6725
Mälardalen University, Department of Innovation, Design and Product Development.ORCID iD: 0000-0001-5269-3900
2008 (English)In: RTCSA 2008: 14TH IEEE INTERNATIONAL CONFERENCE ON EMBEDDED AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS - PROCEEDINGS, 2008, p. 337-346Conference paper, Published paper (Refereed)
Abstract [en]

Real-time systems typically have to satisfy complex requirements, mapped to the task attributes, eventually guaranteed by the underlying scheduler. These systems consist of a mix of hard and soft tasks with varying criticality as well as associated fault tolerance requirements. Additionally, the relative criticality of tasks could undergo changes during the evolution of the system. Time redundancy techniques are often preferred in many embedded applications and, hence, it is extremely important to devise appropriate methodologies for scheduling real-time tasks under error assumptions. In this paper, we propose a methodology to provide a priori guarantees in fixed priority scheduling (FPS) such that the system will be able to tolerate one error per every critical task instance. We do so by using Integer Linear Programming (ILP) to derive task attributes that guarantee re-execution of every critical task instance before its deadline, while keeping the associated costs minimized. We illustrate the effectiveness of our approach, in comparison with fault tolerant (FT) adaptations of the well-known rate monotonic (RM), by simulations.

Place, publisher, year, edition, pages
2008. p. 337-346
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-5919DOI: 10.1109/RTCSA.2008.6ISI: 000260407600036Scopus ID: 2-s2.0-53549084077ISBN: 978-0-7695-3349-0 (print)OAI: oai:DiVA.org:mdh-5919DiVA, id: diva2:218087
Conference
14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications Location: Kaohsiung, TAIWAN Date: AUG 25-27, 2008
Available from: 2009-05-19 Created: 2009-05-19 Last updated: 2013-12-03Bibliographically approved
In thesis
1. New Strategies for Ensuring Time and Value Correctness in Dependable Real-Time Systems
Open this publication in new window or tab >>New Strategies for Ensuring Time and Value Correctness in Dependable Real-Time Systems
2009 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Dependable real-time embedded systems are typically composed of a number of heterogeneous computing nodes, heterogeneous networks that connect them and tasks with multiple criticality levels allocated to the nodes. The heterogeneous nature of the hardware, results in a varying vulnerability to different types of hardware failures. For example, a computing node with effective shielding shows higher resistance to transient failures caused by environmental conditions such as radiation or temperature changes than an unshielded node. Similarly, resistance to permanent failures can vary depending on the manufacturing procedures used. Vulnerability to different types of errors of a task which may lead to a system failure, depends on several factors, such as the hardware on which the task runs and communicates, the software architecture and the implementation quality of the software, and varies from task to task. This variance, as well as the different criticality levels and real-time requirements of tasks, necessitate novel fault-tolerance approaches to be developed and used, in order to meet the stringent dependability requirements of resource-constrained real-time systems.

 

In this thesis, the major contribution is four-fold. Firstly, we describe an error classification for real-time embedded systems and address error propagation aspects. The goal of this work is to perform the analysis on a given system, in order to find bottlenecks in satisfying dependability requirements and to provide guidelines on the usage of appropriate error detection and fault tolerance mechanisms.

 

Secondly, we present a time-redundancy approach to provide a priori guarantees in fixed-priority scheduling (FPS) such that the system will be able to tolerate one value error per every critical task instance by re-execution of every critical task instance or execution of alternate tasks before deadlines, while keeping the associated costs minimized.

 

Our third contribution is a new approach, Voting on Time and Value (VTV) which extends the N-modular redundancy approach by explicitly considering both value and timing errors, such that correct value is produced at a correct time, under specified assumptions. We illustrate our voting approach by instantiating it in the context of the well-known triple modular redundancy (TMR) approach. Further, we present a generalized voting algorithm targeting NMR that enables a high degree of customization from the user perspective.

 

Finally, we propose a novel cascading redundancy approach within a generic fault tolerant scheduling framework. The proposed approach is capable of tolerating errors with a wider coverage (with respect to error frequency and error types) than our proposed time and space redundancy approaches in isolation, allows tasks with mixed criticality levels, is independent of the scheduling technique and, above all, ensures that every critical task instance can be feasibly replicated in both time and/or space. The fault-tolerance techniques presented in this thesis address various different error scenarios that can be observed in real-time embedded systems with respect to the types of errors and frequency of occurrence, and can be used to achieve the ultra-high levels of dependability which is required in many critical systems.

Place, publisher, year, edition, pages
Västerås: Mälardalens Högskola, 2009
Series
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 104
National Category
Computer Sciences
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-5925 (URN)978-91-86135-28-7 (ISBN)
Presentation
2009-06-11, Gamma, Västerås, 15:30 (English)
Opponent
Supervisors
Projects
PROGRESS
Available from: 2009-05-19 Created: 2009-05-19 Last updated: 2018-01-13Bibliographically approved

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Dobrin, RaduAysan, HüseyinPunnekkat, Sasikumar

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