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CLAMP: Criticality Aware Coherency Protocol for Locked Multi-level Caches in Multi-core Processors
ITS Pilani, K. K. BIRLA Goa Campus, Goa, India.
ITS Pilani, K. K. BIRLA Goa Campus, Goa, India.
BMS Institute of Technology and Management, Doddaballapur, Main Road, Karnataka, Avalahalli, Yelahanka, Bengaluru, India.
ITS Pilani, K. K. BIRLA Goa Campus, Goa, India.
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2023 (English)In: Lect. Notes Networks Syst., Springer Science and Business Media Deutschland GmbH , 2023, p. 371-381Conference paper, Published paper (Refereed)
Abstract [en]

Cyber-physical systems that combine sensing, computing, control and networking with physical items and infrastructure, such as automotive, avionics and robotics, are rapidly becoming mixed criticality systems (MCS). The increasing expectations for computing ability and predictable temporal behaviour of these systems necessitate substantial enhancements in their memory subsystem architecture. The use of locked caches to have predictable execution time is one such optimization. There is no comprehensive method in order to manage coherency in locked caches in any of the current cache coherence protocols like MOESI. CLAMP—A criticality aware coherency protocol for locked multi-level caches in multi-core processors is an updated variant of MOESI and as an extension of MOESIL, to improve the data consistency of locked caches. The work CLAMP proposes an improvised locked cache coherence protocol for multiple levels of cache in multi-core MCS, whereas MOESIL is restricted to two-level cache architecture. Experiments using real-time benchmark programs on CACOSIM reveal an average cache miss rate reduction of 18% for high-criticality jobs.

Place, publisher, year, edition, pages
Springer Science and Business Media Deutschland GmbH , 2023. p. 371-381
Keywords [en]
Cache locking, Cache optimization, Cache partitioning, Hierarchical cache architecture, Mixed criticality systems, Multi-core/many core architecture, Cache memory, Criticality (nuclear fission), Embedded systems, Hierarchical systems, Internet protocols, Locks (fasteners), Memory architecture, Cache architecture, Hierarchical caches, Many-core architecture, Mixed-criticality systems, Multi-cores, Network architecture
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Computer and Information Sciences
Identifiers
URN: urn:nbn:se:mdh:diva-64431DOI: 10.1007/978-981-99-0483-9_30Scopus ID: 2-s2.0-85171348053ISBN: 9789819904822 (print)OAI: oai:DiVA.org:mdh-64431DiVA, id: diva2:1803401
Conference
Lecture Notes in Networks and Systems
Available from: 2023-10-09 Created: 2023-10-09 Last updated: 2023-10-09Bibliographically approved

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Punnekkat, Sasikumar

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