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Investigating interoperability in Digital Twin Architectures.
Mälardalen University, School of Innovation, Design and Engineering, Innovation and Product Realisation.ORCID iD: 0000-0003-3683-8174
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-8027-0611
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1687-930X
(English)Manuscript (preprint) (Other academic)
Abstract [en]

Digital Twin architectures comprise multi-integrated building blocks, which include components for data acquisition, management, and processing. Effective and error-prone data exchange between building blocks of the digital twin is the foundation of its successful implementation reflecting the growing importance of interoperability (i.e. ability of systems to exchange data and make use of the data that is exchanged). This paper examines communication technologies (such as protocols and standards) used for the development of digital twins for manufacturing identifying interfaces between physical counterparts and digital twins, as well as between different digital twins, with the ultimate goal of analysing data interoperability concerns. At this end, we use the assessment model “Levels of Conceptual Interoperability Model” to define the applicable levels of interoperability for the identified interfaces and discuss the trade-offs for reaching higher levels of interoperability.

National Category
Computer Systems
Research subject
Computer Science
Identifiers
URN: urn:nbn:se:mdh:diva-62421OAI: oai:DiVA.org:mdh-62421DiVA, id: diva2:1755587
Available from: 2023-05-08 Created: 2023-05-08 Last updated: 2023-05-09Bibliographically approved
In thesis
1. Towards a Standards-Based Architecture for Digital Twins Facilitating Interoperability
Open this publication in new window or tab >>Towards a Standards-Based Architecture for Digital Twins Facilitating Interoperability
2023 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Digital transformation is rapidly changing the business landscape, compellingcompanies to invest in it due to its several benefits, such as reduced time-to-value, improved quality, and the ability to overcome hardware limitations. Aprominent technology enabling digital transformation is digital twin. A digitaltwin is a virtual representation of a physical asset, system, or process, usedfor monitoring and controlling purposes. Implementing digital twins requirestackling challenging engineering tasks such as establishing accurate digitalrepresentations of physical systems or ensuring live data synchronization. Suchchallenges are exacerbated by a lack of research on software architecturesthat meet required quality attributes, their actual implementation, and otherengineering tasks. Software architectures serve as a blueprint and foundationfor building software-intensive systems that meet specific requirements. Theyprovide a comprehensive overview of a system components, their properties,and relationships. Reference architectures, which are based on establishedbest practices in a given domain, help in reasoning about a class of softwarearchitectures and facilitate the engineering of software-intensive systems such asdigital twins. Given the above premises, the ultimate goal of this research is todefine a standard-based reference architecture for digital twins in manufacturingto improve interoperability. We use existing standards as common ground tofacilitate technology transfer between academia and industry. In addition, wefocus on interoperability as it is a crucial quality attribute affecting the functionalsuitability and performance efficiency of digital twins.

Place, publisher, year, edition, pages
Västerås: Mälardalens universitet, 2023
Series
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 342
National Category
Computer Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-62423 (URN)978-91-7485-599-9 (ISBN)
Presentation
2023-06-20, Kappa, Mälardalens universitet, Västerås, 09:15 (English)
Opponent
Supervisors
Available from: 2023-05-09 Created: 2023-05-08 Last updated: 2023-05-30Bibliographically approved

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Ferko, EnxhiBucaioni, AlessioBehnam, Moris

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CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf