https://www.mdu.se/

mdu.sePublications
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories
Univ Tehran, Tehran, Iran..
Univ Tehran, Tehran, Iran..
King Mongkuts Univ Technol, Bangkok, Thailand..
Univ Tehran, Tehran, Iran..
Show others and affiliations
2020 (English)In: IEEE COMPUTER ARCHITECTURE LETTERS, E-ISSN 1556-6056, Vol. 19, no 1, p. 80-83Article in journal (Refereed) Published
Abstract [en]

Data copy is a widely-used memory operation in many programs and operating system services. In conventional computers, data copy is often carried out by two separate read and write transactions that pass data back and forth between the DRAM chip and the processor chip. Some prior mechanisms propose to avoid this unnecessary data movement by using the shared internal bus in the DRAM chip to directly copy data within the DRAM chip (e.g., between two DRAM banks). While these methods exhibit superior performance compared to conventional techniques, data copy across different DRAM banks is still greatly slower than data copy within the same DRAM bank. Hence, these techniques have limited benefit for the emerging 3D-stacked memories (e.g., HMC and HBM) that contain hundreds of DRAM banks across multiple memory controllers. In this paper, we present Network-on-Memory (NoM), a lightweight inter-bank data communication scheme that enables direct data copy across both memory banks of a 3D-stacked memory. NoM adopts a TDM-based circuit-switching design, where circuit setup is done by the memory controller. Compared to state-of-the-art approaches, NoM enables both fast data copy between multiple DRAM banks and concurrent data transfer operations. Our evaluation shows that NoM improves the performance of data-intensive workloads by 3.8X and 75 percent, on average, compared to the baseline conventional 3D-stacked DRAM architecture and state-of-the-art techniques, respectively.

Place, publisher, year, edition, pages
IEEE COMPUTER SOC , 2020. Vol. 19, no 1, p. 80-83
Keywords [en]
Memory network, 3D-stacked memory, circuit switching, data copy, memory systems
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:mdh:diva-49432DOI: 10.1109/LCA.2020.2990599ISI: 000543277600002Scopus ID: 2-s2.0-85084060594OAI: oai:DiVA.org:mdh-49432DiVA, id: diva2:1454201
Available from: 2020-07-15 Created: 2020-07-15 Last updated: 2022-04-22Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full textScopus

Authority records

Daneshtalab, Masoud

Search in DiVA

By author/editor
Daneshtalab, Masoud
By organisation
Embedded Systems
Computer and Information Sciences

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 22 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf