https://www.mdu.se/

High-level synthesis (HLS) is now widely used to implement heterogeneous systems. It was invented to enable designers to use high-level languages such as C or C++. It makes it possible for the software developers to move their implementations to an FPGA or ASIC without having to know the hardware details. HLS tools only convert a high-level software program to a hardware implementation, and reliability and performance measures must be taken by the designer prior to feeding the program to the tool. In this thesis, we propose methods to improve the reliability and performance aspects of heterogeneous systems generated with the help of an HLS. We first propose methods to improve the reliability of the generated circuit either through utilizing pre-existing assertion statements for high-speed design testing and post-synthesis monitoring or by defining a generic redundancy method for self-healing hardware modules. Then, we propose an automatic toolchain to guide the HLS tool to generate a high-performance circuit.