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Characterization of Shared Resource Contention in Multi-core Systems
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
2019 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Multi-core computers are infamous for being hard to use in time-critical systems due to execution-time variations as an effect of shared resource contention. In this thesis we study the problem of shared resource contention which occurs when multiple applications executing on different cores do not have exclusive ownership of a shared resource. We investigate performance variations of parallel tasks in multi-core systems and present a method to pinpoint the source of the resource contention using existing hardware performance counters. Furthermore, we investigate methods to mitigate performance variations using resource isolation techniques. We present a methodology for verifying isolation and tested the achieved isolation using the Jailhouse hypervisor. We further investigate shared cache memory isolation techniques using a page coloring tool called PALLOC. Page-coloring is used for partitioning the cache, assigning specific cache lines to specific processes. Page coloring can however cause system performance degradation since it decreases the total amount of cache memory available for each process. Finally, we propose a dynamic partitioning assignment policy which assigns cache partitions to a process according to an adaptive model based on the process performance. The general conclusion from our investigations is that a large body of applications can suffer from shared resource contention and that techniques for mitigating resource contention are in dire need. Our methods measure and characterise applications, identifies resource contention and finally study isolation techniques.  

Place, publisher, year, edition, pages
Västerås: Mälardalen University , 2019. , p. 160
Series
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 287
National Category
Computer Systems
Research subject
Computer Science
Identifiers
URN: urn:nbn:se:mdh:diva-45932ISBN: 978-91-7485-449-7 (print)OAI: oai:DiVA.org:mdh-45932DiVA, id: diva2:1369134
Presentation
2019-12-17, Paros, Mälardalens högskola, Västerås, 13:15 (English)
Opponent
Supervisors
Available from: 2019-11-11 Created: 2019-11-11 Last updated: 2019-11-18Bibliographically approved
List of papers
1. Investigating execution-characteristics of feature-detection algorithms
Open this publication in new window or tab >>Investigating execution-characteristics of feature-detection algorithms
2017 (English)In: IEEE Conference on Emerging Technologies and Factory Automation, ISSN 1946-0740, E-ISSN 1946-0759, Vol. Part F134116, p. 1-4Article in journal (Refereed) Published
Abstract [en]

We discuss how to obtain information of execution characteristics, such as parallelizability and memory utilization, with the final aim to improve the performance and predictability of feature and corner detection algorithms for use in e.g. robotics and autonomous machines. Our aim is to obtain a better understanding of how computer vision algorithms use hardware resources and how to improve the time predictability and execution time of such algorithms when executing on multi-core CPUs. We evaluate a fork-join model applicable to feature detection algorithms and present a method for measuring how well the algorithm performance correlates with hardware resource usage. We have applied our method to the Featured from Accelerated Segment Test (FAST) algorithm. Our characterization of FAST reveals that it is an algorithm with excellent parallelism opportunities, resulting in an almost linear speed-up per core. Our measurements also reveal that the performance of FAST correlates very little with the number number of misses in the L1 data cache, L1 instruction cache, data translation lookaside buffer and L2 cache. Thus, the FAST algorithm will not have a negative effect on the execution time when the input data fits in the L2 cache. 

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc., 2017
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-38918 (URN)10.1109/ETFA.2017.8247758 (DOI)000427812000193 ()2-s2.0-85044481799 (Scopus ID)
Conference
22nd IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), Limassol, CYPRUS, SEP 12-15, 2017
Available from: 2018-04-05 Created: 2018-04-05 Last updated: 2019-11-11Bibliographically approved
2. Measurement-based evaluation of data-parallelism for OpenCV feature-detection algorithms
Open this publication in new window or tab >>Measurement-based evaluation of data-parallelism for OpenCV feature-detection algorithms
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2018 (English)In: Staying Smarter in a Smartening World COMPSAC'18, 2018, p. 701-710Conference paper, Published paper (Refereed)
Abstract [en]

We investigate the effects on the execution time, shared cache usage and speed-up gains when using data-partitioned parallelism for the feature detection algorithms available in the OpenCV library. We use a data set of three different images which are scaled to six different sizes to exercise the different cache memories of our test architectures. Our measurements reveal that the algorithms using the default settings of OpenCV behave very differently when using data-partitioned parallelism. Our investigation shows that the executions of the algorithms SURF, Dense and MSER correlate to L3-cache usage and they are therefore not suitable for data-partitioned parallelism on multi-core CPUs. Other algorithms: BRISK, FAST, ORB, HARRIS, GFTT, SimpleBlob and SIFT, do not correlate to L3-cache in the same extent, and they are therefore more suitable for data-partitioned parallelism. Furthermore, the SIFT algorithm provides the most stable speed-up, resulting in an execution between 3 and 3.5 times faster than the original execution time for all image sizes. We also have evaluated the hardware resource usage by measuring the algorithm execution time simultaneously with the L3-cache usage. We have used our measurements to conclude which algorithms are suitable for parallelization on hardware with shared resources.

Keywords
Multi-core, OpenCV, Cache
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-40855 (URN)10.1109/COMPSAC.2018.00105 (DOI)2-s2.0-85055434865 (Scopus ID)9781538626665 (ISBN)
Conference
42nd IEEE Computer Software and Applications Conference, COMPSAC 2018; Tokyo; Japan; 23 July 2018 through 27 July 2018
Projects
DPAC - Dependable Platforms for Autonomous systems and Control
Available from: 2018-09-20 Created: 2018-09-20 Last updated: 2019-11-11Bibliographically approved
3. Testing Performance-Isolation in Multi-Core Systems
Open this publication in new window or tab >>Testing Performance-Isolation in Multi-Core Systems
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2019 (English)Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we present a methodology to be used for quantifying the level of performance isolation for a multi-core system. We have devised a test that can be applied to breaches of isolation in different computing resources that may be shared between different cores. We use this test to determine the level of isolation gained by using the Jailhouse hypervisor compared to a regular Linux system in terms of CPU isolation, cache isolation and memory bus isolation. Our measurements show that the Jailhouse hypervisor provides performance isolation of local computing resources such as CPU. We have also evaluated if any isolation could be gained for shared computing resources such as the system wide cache and the memory bus controller. Our tests show no measurable difference in partitioning between a regular Linux system and a Jailhouse partitioned system for shared resources. Using the Jailhouse hypervisor provides only a small noticeable overhead when executing multiple shared-resource intensive tasks on multiple cores, which implies that running Jailhouse in a memory saturated system will not be harmful. However, contention still exist in the memory bus and in the system-wide cache.

National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-45947 (URN)10.1109/COMPSAC.2019.00092 (DOI)978-1-7281-2607-4 (ISBN)
Conference
43rd IEEE Annual Computer Software and Applications Conference, COMPSAC 2019; Milwaukee; United States; 15 July 2019 through 19 July 2019
Available from: 2019-11-11 Created: 2019-11-11 Last updated: 2019-11-11Bibliographically approved
4. Run-time Cache-Partition Controller for Multi-core Systems
Open this publication in new window or tab >>Run-time Cache-Partition Controller for Multi-core Systems
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2019 (English)Conference paper, Published paper (Refereed)
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-45949 (URN)
Conference
In 45th Annual Conference of the IEEE Industrial Electronics Society (IECON), 2019
Available from: 2019-11-11 Created: 2019-11-11 Last updated: 2019-11-11Bibliographically approved

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Danielsson, Jakob

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