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LRTM: Life-time and Reliability-aware Task Mapping Approach for Heterogeneous Multi-core Systems
University of Tehran, Tehran, Iran.
University of Tehran, Tehran, Iran.
University of Tehran, Tehran, Iran.
University of Tehran, Tehran, Iran.
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2018 (English)In: 2018 11th International Workshop on Network on Chip Architectures, NoCArc 2018 - In conjunction with the 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018, Institute of Electrical and Electronics Engineers Inc. , 2018, article id 8541223Conference paper, Published paper (Refereed)
Abstract [en]

Technology scaling, increasing number of components in a single chip, and aging effects have brought severe reliability challenges in multi-core platforms. They are more susceptible to faults, both permanent and transient. This paper proposes a Lifetime and Reliability-aware Task Mapping (LRTM) approach to many-core platforms with heterogeneous cores. It tries to confront both transient faults and wear-out failures. Our proposed approach maintains the predefined level of reliability for the task graph in presence of transient faults over the whole lifetime of the system. LRTM uses replication technique with minimum replica overhead, maximum achievable performance, and minimum temperature increase to confront transient faults while increasing the lifetime of the system. Besides, LRTM specifies task migration plans with the minimum overhead using a novel heuristic approach on the occurrence of permanent core failures due to wear-out mechanisms. Task migration scenarios are used during run-time to increase the lifetime of the system while maintaining reliability threshold of the system. Results show the effectiveness of LRTM improves for bigger mesh sizes and higher reliability thresholds. Simulation results obtained from real benchmarks show the proposed approach decreases design-time calculation up to 4371% compared to exhaustive exploration while achieving lifetime negligibly lower than the exhaustive solution (up to 5.83%). LRTM also increases lifetime about 3% compared to other heuristic approaches in the literature.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc. , 2018. article id 8541223
National Category
Computer and Information Sciences
Identifiers
URN: urn:nbn:se:mdh:diva-42406DOI: 10.1109/NOCARC.2018.8541223Scopus ID: 2-s2.0-85059981160ISBN: 9781538685525 (print)OAI: oai:DiVA.org:mdh-42406DiVA, id: diva2:1282373
Conference
2018 11th International Workshop on Network on Chip Architectures (NoCArc)
Available from: 2019-01-24 Created: 2019-01-24 Last updated: 2019-06-04Bibliographically approved

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Daneshtalab, Masoud

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Citation style
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