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Reconfigurable Network-on-Chip for 3D Neural Network Accelerators
Islamic Azad University, Tehran, Iran.
University of Tehran and IPM School of ComputerScience, Tehran, Iran.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
Islamic Azad University, Tehran, Iran.
2018 (English)In: 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018, Institute of Electrical and Electronics Engineers Inc. , 2018Conference paper, Published paper (Refereed)
Abstract [en]

Parallel hardware accelerators for large-scale neural networks typically consist of several processing nodes, arranged as a multi- or many-core system-on-chip, connected by a network-on-chip (NoC). Recent proposals also benefit from the emerging 3D memory-on-logic architectures to provide sufficient bandwidth for neural networks. Handling the heavy traffic between neurons and memory and also the multicast-based inter-neuron traffic, which often varies over time, is the most challenging design consideration for the networks-on-chip in such accelerators. To address these issues, a reconfigurable network-on-chip architecture for 3D memory-on-logic neural network accelerators is presented in this paper. The reconfigurable NoC can adapt its topology to the on-chip traffic patterns. It can be also configured as a tree-like structure to support multicast-based neuron-to-neuron and memory-to-neuron traffic of neural networks. The evaluation results show that the proposed architecture can better manage the multicast-based traffic of neural networks than some state-of-the-art topologies and considerably increase throughput and power efficiency. 

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc. , 2018.
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:mdh:diva-41506DOI: 10.1109/NOCS.2018.8512170Scopus ID: 2-s2.0-85057297781ISBN: 9781538648933 (print)OAI: oai:DiVA.org:mdh-41506DiVA, id: diva2:1268527
Conference
12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018, 4 October 2018 through 5 October 2018
Available from: 2018-12-06 Created: 2018-12-06 Last updated: 2018-12-06Bibliographically approved

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Daneshtalab, Masoud

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CiteExportLink to record
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Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
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  • de-DE
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Output format
  • html
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  • asciidoc
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