A Customized Processing-in-Memory Architecture for Biological Sequence Alignment
2018 (English)In: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, Institute of Electrical and Electronics Engineers Inc. , 2018, article id 8445124Conference paper, Published paper (Refereed)
Abstract [en]
Sequence alignment is the most widely used operation in bioinformatics. With the exponential growth of the biological sequence databases, searching a database to find the optimal alignment for a query sequence (that can be at the order of hundreds of millions of characters long) would require excessive processing power and memory bandwidth. Sequence alignment algorithms can potentially benefit from the processing power of massive parallel processors due their simple arithmetic operations, coupled with the inherent fine-grained and coarse-grained parallelism that they exhibit. However, the limited memory bandwidth in conventional computing systems prevents exploiting the maximum achievable speedup. In this paper, we propose a processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications. The design is composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture. Experimental results show that the proposed architecture results in up to 2.4x speedup and 41% reduction in power consumption, compared to a processor-side parallel implementation.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers Inc. , 2018. article id 8445124
Keywords [en]
Accelerator, Processing-in-memory, Sequence Alignment, Alignment, Bandwidth, Bioinformatics, Computation theory, Dynamic random access storage, Parallel processing systems, Particle accelerators, Query processing, 3d dram architectures, Bioinformatics applications, Biological sequence alignment, Massive parallel processors, Parallel implementations, Processing in memory, Proposed architectures, Sequence alignments, Memory architecture
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:mdh:diva-41018DOI: 10.1109/ASAP.2018.8445124ISI: 000447635800027Scopus ID: 2-s2.0-85053445393ISBN: 9781538674796 (print)OAI: oai:DiVA.org:mdh-41018DiVA, id: diva2:1251539
Conference
29th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2018, 10 July 2018 through 12 July 2018
2018-09-272018-09-272022-11-08Bibliographically approved