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Analysis and Design of Low-Phase-Noise Integrated Voltage-Controlled Oscillators for Wide-Band RF Front-Ends
Mälardalen University, Department of Computer Science and Electronics.
2006 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

The explosive development of wireless communication services creates a demand for more flexible and cost-effective communication systems that offer higher data rates. The obvious trend towards small-size and ultra low power systems, in combination with the ever increasing number of applications integrated in a single portable device, tightens the design constraints at hardware and software level. The integration of current mobile systems with the third generation systems exemplifies and emphasizes the need of monolithic multi-band transceivers. A long term goal is a software defined radio, where several communication standards and applications are embedded and reconfigured by software. This motivates the need for highly flexible and reconfigurable analog radio frequency (RF) circuits that can be fully integrated in standard low-cost complementary metal-oxide-semiconductor (CMOS) technologies.

In this thesis, the Voltage-Controlled Oscillator (VCO), one of the main challenging RF circuits within a transceiver, is investigated for today’s and future communication systems. The contributions from this work may be divided into two parts. The first part exploits the possibility and design related issues of wide-band reconfigurable integrated VCOs in CMOS technologies. Aspects such as frequency tuning, power dissipation and phase noise performance are studied and design oriented techniques for wide-band circuit solutions are proposed. For demonstration of these investigations several fully functional wide-band multi-GHz VCOs are implemented and characterized in a 0.18µm CMOS technology.

The second part of the thesis concerns theoretical analysis of phase noise in VCOs. Due to the complex process of conversion from component noise to phase noise, computer aided methods or advanced circuit simulators are usually used for evaluation and prediction of phase noise. As a consequence, the fundamental properties of different noise sources and their impact on phase noise in commonly adopted VCO topologies have so far not been completely described. This in turn makes the optimization process of integrated VCOs a very complex task. To aid the design and to provide a deeper understanding of the phase noise mechanism, a new approach based on a linear time-variant model is proposed in this work. The theory allows for derivation of analytic expressions for phase noise, thereby, providing excellent insight on how to minimize and optimize phase noise in oscillators as a function of circuit related parameters. Moreover, it enables a fair performance comparison of different oscillator topologies in order to ascertain which structure is most suitable depending on the application of interest. The proposed method is verified with very good agreement against both advanced circuit simulations and measurements in CMOS and bipolar technologies. As a final contribution, using the knowledge gained from the theoretical analysis, a fully integrated 0.35µm CMOS VCO with superior phase noise performance and power dissipation is demonstrated.

Place, publisher, year, edition, pages
Västerås: Institutionen för Datavetenskap och Elektronik , 2006. , p. 166
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 25
Keywords [en]
Electronic
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Elektronik
Identifiers
URN: urn:nbn:se:mdh:diva-88ISBN: 91–85485–05-5 OAI: oai:DiVA.org:mdh-88DiVA, id: diva2:121535
Public defence
2006-01-27, Beta, 14:00
Opponent
Supervisors
Available from: 2006-01-01 Created: 2006-01-01
List of papers
1. A Low Power Wide-Band CMOS VCO for Multi-Standard Radios
Open this publication in new window or tab >>A Low Power Wide-Band CMOS VCO for Multi-Standard Radios
2004 (English)In: Proceedings - 2004 IEEE Radio and Wireless Conference, RAWCON, 2004, p. 79-82Conference paper, Published paper (Other academic)
Abstract [en]

This paper presents a single monolithic wide band VCO for multi-standard radios. Analysis on a differential switched capacitor circuit is performed. Its impact on phase noise and power dissipation is especially addressed. The analysis is demonstrated and verified in a fully integrated CMOS VCO that consumes 2.7 mA from a 1.8 V supply and operates with a wide frequency band from 3.5 - 5.3 GHz. The measured phase noise is less than -110 dBc/Hz at 1 MHz offset within the entire tuning range.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4233 (URN)10.1109/RAWCON.2004.1389076 (DOI)000224588200021 ()2-s2.0-14844332709 (Scopus ID)0-7803-8451-2 (ISBN)
Conference
2004 IEEE Radio and Wireless Conference, RAWCON; Atlanta, GA; United States; 19 September 2004 through 22 September 2004
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2016-10-31Bibliographically approved
2. Design of a dual-band 5/2.4 GHZ CMOS VCO for 802.11 A/B/G WLAN transceivers
Open this publication in new window or tab >>Design of a dual-band 5/2.4 GHZ CMOS VCO for 802.11 A/B/G WLAN transceivers
2004 (English)In: IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, Volume 1, 2004, 2004, p. 429-432Conference paper, Published paper (Other academic)
Abstract [en]

A dual-band CMOS VCO with a divide-by-two circuit, operating between 4.7-6.2/2.35-3.1 GHz is demonstrated in a 0.35mum process. The VCO phase noise is reduced by matching the transconductance and impedance of the active devices. By using a divide-by-two stage quadrature signals for the 802.11 b/g standards are obtained. The VCO is optimized for low phase noise and small amplitude variations across the tuning range. The phase noise levels are less than -116.5 and -126 dBc/Hz at 1 MHz offset in the upper and lower frequency band respectively.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4234 (URN)10.1109/APCCAS.2004.1412788 (DOI)2-s2.0-21644435786 (Scopus ID)0-7803-8660-4 (ISBN)
Conference
2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology; Tainan; Taiwan; 6 December 2004 through 9 December 2004
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2015-07-29Bibliographically approved
3. An Improved Phase-Frequency Detector with Extended Frequency Capability
Open this publication in new window or tab >>An Improved Phase-Frequency Detector with Extended Frequency Capability
2004 (English)In: Midwest Symposium on Circuits and SystemsVolume 1, 2004, 2004, p. 181-184Conference paper, Published paper (Other academic)
Abstract [en]

An improved high-performance dynamic-logic tri-state phase-frequency detector architecture is derived through extensive time domain analysis. In particular, the impact of the reset time's on the maximum operating frequency and phase characteristics of the phase-frequency detector is discussed. The analysis is verified for the presented improved architecture and excellent agreement between theory and simulation is observed. The phase-frequency detector architecture is proven to function for supply voltages below 1 V and has an increased frequency capability of more than 20% with a power consumption of 10 μW at 500 MHz input frequency.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4235 (URN)10.1109/MWSCAS.2004.1353927 (DOI)2-s2.0-11144248886 (Scopus ID)0-7803-8346-X (ISBN)
Conference
2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings; Hiroshima; Japan; 25 July 2004 through 28 July 2004
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2015-07-29Bibliographically approved
4. A High-Performance 1V Dead-Zone Free Phase-Frequency Detector with Minimized Blind-zone
Open this publication in new window or tab >>A High-Performance 1V Dead-Zone Free Phase-Frequency Detector with Minimized Blind-zone
2004 (English)In: Proceedings of Swedish System-on-Chip Conference (SSoC), 2004Conference paper, Published paper (Other academic)
Identifiers
urn:nbn:se:mdh:diva-4236 (URN)
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2015-07-29Bibliographically approved
5. Phase Noise and Amplitude Issues of a Wide Band VCO Utilizing a Switched Tuning Resonator
Open this publication in new window or tab >>Phase Noise and Amplitude Issues of a Wide Band VCO Utilizing a Switched Tuning Resonator
2005 (English)In: Proceedings - IEEE International Symposium on Circuits and Systems, 2005, p. 2691-2694Conference paper, Published paper (Other academic)
Abstract [en]

A 3.5-5.3 GHz, low phase noise CMOS VCO with switched tuning for multi-standard radios is presented in this paper. Design of low phase noise and small amplitude variations across the operating frequency is shown to be important aspects in wide-band VCOs. An analytic expression for the output amplitude of the VCO is derived as a function of the switched capacitor resonator Q. The linear-time variant model was used for prediction of the phase noise and for deciding a proper tank current to achieve the minimum phase noise and amplitude variations across the frequency range. The results are verified in a fully integrated 0.18μm VCO with measured phase noise levels of less than -115 dBc/Hz at 1 MHz offset from the carrier while dissipating 6 mW of power. 

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4237 (URN)10.1109/ISCAS.2005.1465181 (DOI)000232002402196 ()2-s2.0-33847709786 (Scopus ID)
Conference
IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005; Kobe; Japan; 23 May 2005 through 26 May 2005
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2015-07-28Bibliographically approved
6. A Reconfigurable CMOS VCO with and Automatic Amplitude Controller for Multi-Band RF Front-Ends
Open this publication in new window or tab >>A Reconfigurable CMOS VCO with and Automatic Amplitude Controller for Multi-Band RF Front-Ends
2005 (English)In: Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005, p. 95-98Conference paper, Published paper (Other academic)
Abstract [en]

A fully integrated reconfigurable 3.6-6.0 GHz 0.18μm CMOS VCO with an automatic amplitude controller (AAC) for multi-standard front-ends is proposed. Due to the wide tuning range, utilizing mixed tuning technique, large amplitude variations over the band are observed. Thus a novel low noise AAC is implemented to stabilize the amplitude regardless of operation frequency. Measurements are performed both with and without the AAC loop active, showing that the AAC loops noise contributions are very small. The circuit displays phase noise levels of-124 dBc/Hz or less at 3 MHz offset within the entire frequency band while consuming 7.7-12.2 mW of power. The relative amplitude variation over the frequency band are 100 mV.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4238 (URN)10.1109/ECCTD.2005.1522918 (DOI)000234406900024 ()2-s2.0-33749065410 (Scopus ID)9780780390669 (ISBN)
Conference
2005 European Conference on Circuit Theory and Design; Cork; Ireland; 28 August 2005 through 2 September 2005
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2018-08-22Bibliographically approved
7. A Low-Phase-Noise Wide-Band CMOS Quadrature VCO for Multi-Standard RF Front-Ends
Open this publication in new window or tab >>A Low-Phase-Noise Wide-Band CMOS Quadrature VCO for Multi-Standard RF Front-Ends
2005 (English)In: Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, 2005, p. 539-542Conference paper, Published paper (Other academic)
Abstract [en]

A low phase noise CMOS LC quadrature VCO (QVCO) with a wide frequency range of 3.6-5.6 GHz, designed in a standard 0.18 μm process for multi-standard front-ends, is presented. A significant advantage of the topology is the larger oscillation amplitude when compared to other conventional QVCO structures. The QVCO is compared to a double cross-coupled LC-tank differential oscillator, both in theory and experiments, for evaluation of its phase noise, providing a good insight into its performance. The measured data displays up to 2 dBc/Hz lower phase noise in the 1/f2 region for the QVCO, when consuming twice the current of the differential VCO, based on an identical LC-tank. Experimental results on the QVCO show a phase noise level of -127.5 dBc/Hz at 3 MHz offset from a 5.6 GHz carrier while dissipating 8 mA of current, resulting in a figure of merit of 181.3 dBc/Hz.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4239 (URN)10.1109/RFIC.2005.1489868 (DOI)000230541500121 ()2-s2.0-27644584418 (Scopus ID)0-7803-8983-2 (ISBN)
Conference
2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium - Digest of Papers; Long Beach, CA; United States; 12 June 2005 through 14 June 2005
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2018-08-21Bibliographically approved
8. Phase Noise Analysis and Design of a 3-GHz Bipolar Differential Colpitts VCO
Open this publication in new window or tab >>Phase Noise Analysis and Design of a 3-GHz Bipolar Differential Colpitts VCO
2005 (English)In: Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference, 2005, p. 391-394Conference paper, Published paper (Other academic)
Abstract [en]

This paper presents a low-phase-noise differential bipolar Colpitts VCO, implemented in a 0.35μm BiCMOS process. A time-variant phase noise analysis yields closed-form symbolic expressions for the dominant noise sources in the I/f2 phase-noise region. Measurements show a phase noise of -123 dBc/Hz at 1 MHz offset from a 2.8-3.1 GHz carrier, for a figure-of-merit of 183 dBc/Hz. A very good agreement between the derived theoretical formulas, spectreRF simulations, and measurements is observed.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4240 (URN)10.1109/ESSCIR.2005.1541642 (DOI)2-s2.0-33749163514 (Scopus ID)9780780392052 (ISBN)
Conference
ESSCIRC 2005: 31st European Solid-State Circuits Conference; Grenoble; France; 12 September 2005 through 16 September 2005
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2015-07-28Bibliographically approved
9. A 2.3 GHz LC-Tank CMOS VCO with Optimal Phase Noise Performance
Open this publication in new window or tab >>A 2.3 GHz LC-Tank CMOS VCO with Optimal Phase Noise Performance
2006 (English)In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2006, p. 691-700Conference paper, Published paper (Other academic)
Abstract [en]

The phase-noise theory and design of a differential CMOS LC-tank VCO with double switch pair is presented. A formula for the minimum achievable phase noise in the 1/f2 region is derived. The 2.15 to 2.35GHz 0.3μm CMOS VCO has a phase noise of -143.9dBc/Hz at 3MHz offset and draws 4mA from a 2.5V supply.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:mdh:diva-4241 (URN)10.1109/ISSCC.2006.1696108 (DOI)1424400791 (ISBN)978-142440079-9 (ISBN)
Conference
2006 IEEE International Solid-State Circuits Conference, ISSCC; San Francisco, CA; 6 February 2006 through 9 February 2006
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2013-02-06Bibliographically approved
10. A novel 18 GHz 1.3 mW CMOS frequency divider with high input sensitivity
Open this publication in new window or tab >>A novel 18 GHz 1.3 mW CMOS frequency divider with high input sensitivity
2005 (English)In: ISSCS 2005: International Symposium on Signals, Circuits and Systems - Proceedings, 2005, p. 409-412Conference paper, Published paper (Other academic)
Abstract [en]

A novel CMOS high speed divide-by-two circuit with very low power consumption is proposed in this paper. The circuit features very low input capacitance and a wide locking range of 1.5-18 GHz with a power consumption of less than 13 mW at 1.8 V. The input sensitivity of the stage is improved significantly when compared to conventional dynamic loaded high frequency dividers. The concept and design issue of the circuit is presented together with a performance comparison to existing topologies. The idea is demonstrated and verified in a standard 0.18 μm CMOS process through realistic simulations originating from a complete layout using moderately extracted parasitics.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4242 (URN)10.1109/ISSCS.2005.1511264 (DOI)000231532900103 ()2-s2.0-33749043635 (Scopus ID)9780780390294 (ISBN)
Conference
ISSCS 2005: International Symposium on Signals, Circuits and Systems; Iasi; Romania; 14 July 2005 through 15 July 2005
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2018-08-22Bibliographically approved
11. A Comparative Study of CMOS LC VCO Topologies for Wide-Band Multi-Standard Transceivers
Open this publication in new window or tab >>A Comparative Study of CMOS LC VCO Topologies for Wide-Band Multi-Standard Transceivers
2004 (English)In: Midwest Symposium on Circuits and SystemsVolume 3, 2004, 2004, p. 17-20Conference paper, Published paper (Other academic)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4243 (URN)10.1109/MWSCAS.2004.1354280 (DOI)2-s2.0-11144338822 (Scopus ID)0-7803-8346-X (ISBN)
Conference
The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings; Hiroshima; Japan; 25 July 2004 through 28 July 2004
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2015-07-29Bibliographically approved
12. A Study of Phase Noise in Colpitts and LC-tank CMOS Oscillators
Open this publication in new window or tab >>A Study of Phase Noise in Colpitts and LC-tank CMOS Oscillators
2005 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 40, no 5, p. 1107-1118Article in journal (Refereed) Published
Abstract [en]

This paper presents a study of phase noise in CMOS Colpitts and LC-tank oscillators. Closed-form symbolic formulas for the 1/f2 phase-noiseregion are derived for both the Colpitts oscillator (either single-ended or differential) and the LC-tank oscillator, yielding highly accurate results under very general assumptions. A comparison between the differential Colpitts and the LC-tank oscillator is also carried out, which shows that the latter is capable of a 2-dB lower phase-noise flgure-of-merit (FoM) when simplified oscillator designs and ideal MOS models are adopted. Several prototypesof both Colpitts and LC-tank oscillators have been implemented in a 0.35-μm CMOS process. The best performance of the LC-tank oscillatorsshows a phase noise of - 142 dBc/Hz at 3-MHz offset frequency from a 2.9-GHz carrier with a 16-mW power consumption, resulting in an excellent FoM of ∼189 dBc/Hz. For the same oscillation frequency, the FoM displayed by the differential Colpitts oscillators is ∼5 dB lower.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:mdh:diva-4244 (URN)10.1109/JSSC.2005.845991 (DOI)000228773600008 ()2-s2.0-18444372911 (Scopus ID)
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2017-12-14Bibliographically approved
13. Design of a Dual-Band 5/2.5 GHz CMOS VCO for 802.11 a/b/g WLAN Radios
Open this publication in new window or tab >>Design of a Dual-Band 5/2.5 GHz CMOS VCO for 802.11 a/b/g WLAN Radios
2004 (English)In: Proceedings of Swedish System-on-Chip Conference (SSOC), 2004Chapter in book (Other academic)
National Category
Computer Systems
Identifiers
urn:nbn:se:mdh:diva-4245 (URN)
Available from: 2006-01-01 Created: 2006-01-01 Last updated: 2015-07-29Bibliographically approved

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