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Implementation of digital-serial LDI/LDD allpass filters
Mälardalen University, Department of Computer Science and Electronics.
2006 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

In this thesis, digit-serial implementation of recursive digital filters is considered. The theories presented can be applied to any recursive digital filter, and in this thesis we study the lossless discrete integrator (LDI) allpass filter. A brief introduction regarding suppression of limit cycles at finite wordlength conditions is given, and an extended stability region, where the second-order LDI allpass filter is free from quantization limit cycles, is presented.

The realization of digit-serial processing elements, i.e., digit-serial adders and multipliers, is studied. A new digit-serial hybrid adder (DSHA) is presented. The adder can be pipelined to the bit level with a short arithmetic critical path, which makes it well suited when implementing high-throughput recursive digital filters.

Two digit-serial multipliers which can be pipelined to the bit level are considered. It is concluded that a digit-serial/parallelmultiplier based on shift-accumulation(DSAAM) is a good candidate when implementing recursive digital systems, mainly due to low latency. Furthermore, our study shows that low latency will lead to higher throughput and lower power consumption.

Scheduling of recursive digit-serial algorithms is studied. It is concluded that implementation issues such as latency and arithmetic critical path are usually required before scheduling considerations can be made. Cyclic scheduling using digit-serial arithmetics is also considered. It is shown that digit-serial cyclic scheduling is very attractive for high-throughput implementations.

Place, publisher, year, edition, pages
Västerås: Institutionen för Datavetenskap och Elektronik , 2006. , 154 p.
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 23
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Elektronik
Identifiers
URN: urn:nbn:se:mdh:diva-155ISBN: 91-85485-07-1 (print)OAI: oai:DiVA.org:mdh-155DiVA: diva2:120550
Public defence
2006-01-25, Lambda, Västerås, 13:15
Opponent
Available from: 2006-09-06 Created: 2006-09-06
List of papers
1. Digit-serial implementation of LDI/LDD allpass filters
Open this publication in new window or tab >>Digit-serial implementation of LDI/LDD allpass filters
2002 (English)Conference paper, Published paper (Other academic)
Abstract [en]

In this paper we study digit-serial implementation of the general-order lossless discrete integrator/differentiator (LDI/LDD) allpass filter structure. In low-power filter implementation, digit-serialcomputation has been shown to be advantageous compared to bit-serial and parallel arithmetics. Thedigit-serial processing elements are obtained using unfolding techniques. The implementation is compared to a corresponding wave digital (WD) implementation. It is shown in an example that a WD realization requires about 60% and 30% more D flip-flops for pipelining and shimming delays, respectively, than the corresponding LDI/LDD implementation. We also study the sample period of the second-order LDI/LDD allpass filter using different digit sizes and conclude that when the filter is scheduled over a number of sample periods we achieve the shortest sample period

National Category
Engineering and Technology
Identifiers
urn:nbn:se:mdh:diva-4016 (URN)10.1109/ISCAS.2002.1011445 (DOI)0-7803-7448-7 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems, ISCAS 2002, 26 May 2002-29 May 2002, Phoenix-Scottsdale, AZ, United States
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2014-05-30Bibliographically approved
2. A high-speed low-latency digit-serial hybrid adder
Open this publication in new window or tab >>A high-speed low-latency digit-serial hybrid adder
2004 (English)In: Proceedings - IEEE International Symposium on Circuits and Systems, vol. 3 2004, 2004, 217-220 p.Conference paper, Published paper (Other academic)
Abstract [en]

In this paper, we present a new digit-serial hybrid adder. The adder can be pipelined to the bit-level and is, therefore, well suited for high-speed applications. The main advantage of the proposed adder is that it can be implemented with few pipelining stages. We compare speed, area and power consumption for the proposed adder with a digit-serial carry-look-ahead adder and a digit-serial Ladner-Fisher adder. The results show that the delay of the digit-serial hybrid adder is lower than the other adders studied in this paper for digit-sizes up to d = 12. For these digit-sizes the digit-serial hybrid adder has on average 17% smaller critical path than the digit-serial carry-look-ahead adder and 21% smaller critical path than the digit-serial Ladner-Fisher adder.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4017 (URN)10.1109/ISCAS.2004.1328722 (DOI)2-s2.0-4344682862 (Scopus ID)0-7803-8251-X (ISBN)
Conference
2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2015-07-28Bibliographically approved
3. Implementation of bit-level pipelined digit-serial multipliers
Open this publication in new window or tab >>Implementation of bit-level pipelined digit-serial multipliers
2004 (English)In: Report - Helsinki University of Technology, Signal Processing Laboratory, vol. 46, 2004, 2004, 125-128 p.Conference paper, Published paper (Other academic)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4018 (URN)951-22-7065-X (ISBN)
Conference
6th Nordic Signal Processing Symposium, NORSIG 2004; Espoo; Finland; 9 June 2004 through 11 June 2004
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2015-07-28Bibliographically approved
4. Implementation of high-speed digit-serial LDI allpass filters
Open this publication in new window or tab >>Implementation of high-speed digit-serial LDI allpass filters
2005 (English)In: Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005, 249-252 p.Conference paper, Published paper (Other academic)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:mdh:diva-4019 (URN)10.1109/ECCTD.2005.1523107 (DOI)2-s2.0-33749038013 (Scopus ID)9780780390669 (ISBN)
Conference
2005 European Conference on Circuit Theory and Design; Cork; Ireland; 28 August 2005 through 2 September 2005;
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2015-07-28Bibliographically approved
5. Glitch reduction in digit-serial recursive filters using retiming
Open this publication in new window or tab >>Glitch reduction in digit-serial recursive filters using retiming
2005 (English)In: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2005Conference paper, Published paper (Other academic)
Abstract [en]

In this work, we study how retiming can be used to reduce glitches in digit-serial recursive filters. It is a well known fact that glitches can make up a large portion of the dynamic power consumption in digital systems. Digit-serial recursive systems contain registers that can be retimed to reduce the amount of glitches. A second-order digit-serial LDI allpass filter has been implemented to verify this statement. It is shown that retiming can reduce the power consumption with about 20% for small digit-sizes without affecting the throughput of the filter. We also show that introducing a large number of registers in the filter structure will increase the current consumption. This trade-off, between reducing the amount of glitches and the increase in the number of registers, is also considered in this work.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:mdh:diva-4020 (URN)10.1109/ICECS.2005.4633549 (DOI)2-s2.0-56749165576 (Scopus ID)978-997261100-1 (ISBN)
Conference
12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005; Gammarth; 11 December 2005 through 14 December 2005
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2013-01-15Bibliographically approved
6. Implementation of digit-serial LDI allpass filters using cyclic scheduling
Open this publication in new window or tab >>Implementation of digit-serial LDI allpass filters using cyclic scheduling
(English)Manuscript (Other academic)
National Category
Other Engineering and Technologies
Identifiers
urn:nbn:se:mdh:diva-4021 (URN)
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2015-10-12Bibliographically approved
7. LDI/LDD Lattice Filters
Open this publication in new window or tab >>LDI/LDD Lattice Filters
(English)Manuscript (Other academic)
National Category
Other Engineering and Technologies
Identifiers
urn:nbn:se:mdh:diva-4022 (URN)
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2015-10-12Bibliographically approved

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