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LDI/LDD Lattice Filters
Mälardalen University, Department of Computer Science and Electronics.
(English)Manuscript (Other academic)
National Category
Other Engineering and Technologies
Identifiers
URN: urn:nbn:se:mdh:diva-4022OAI: oai:DiVA.org:mdh-4022DiVA: diva2:120549
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2015-10-12Bibliographically approved
In thesis
1. Implementation of digital-serial LDI/LDD allpass filters
Open this publication in new window or tab >>Implementation of digital-serial LDI/LDD allpass filters
2006 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

In this thesis, digit-serial implementation of recursive digital filters is considered. The theories presented can be applied to any recursive digital filter, and in this thesis we study the lossless discrete integrator (LDI) allpass filter. A brief introduction regarding suppression of limit cycles at finite wordlength conditions is given, and an extended stability region, where the second-order LDI allpass filter is free from quantization limit cycles, is presented.

The realization of digit-serial processing elements, i.e., digit-serial adders and multipliers, is studied. A new digit-serial hybrid adder (DSHA) is presented. The adder can be pipelined to the bit level with a short arithmetic critical path, which makes it well suited when implementing high-throughput recursive digital filters.

Two digit-serial multipliers which can be pipelined to the bit level are considered. It is concluded that a digit-serial/parallelmultiplier based on shift-accumulation(DSAAM) is a good candidate when implementing recursive digital systems, mainly due to low latency. Furthermore, our study shows that low latency will lead to higher throughput and lower power consumption.

Scheduling of recursive digit-serial algorithms is studied. It is concluded that implementation issues such as latency and arithmetic critical path are usually required before scheduling considerations can be made. Cyclic scheduling using digit-serial arithmetics is also considered. It is shown that digit-serial cyclic scheduling is very attractive for high-throughput implementations.

Place, publisher, year, edition, pages
Västerås: Institutionen för Datavetenskap och Elektronik, 2006. 154 p.
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 23
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Elektronik
Identifiers
urn:nbn:se:mdh:diva-155 (URN)91-85485-07-1 (ISBN)
Public defence
2006-01-25, Lambda, Västerås, 13:15
Opponent
Available from: 2006-09-06 Created: 2006-09-06

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CiteExportLink to record
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Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
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