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Glitch reduction in digit-serial recursive filters using retiming
Mälardalen University, Department of Computer Science and Electronics.
2005 (English)In: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, 2005Conference paper, Published paper (Other academic)
Abstract [en]

In this work, we study how retiming can be used to reduce glitches in digit-serial recursive filters. It is a well known fact that glitches can make up a large portion of the dynamic power consumption in digital systems. Digit-serial recursive systems contain registers that can be retimed to reduce the amount of glitches. A second-order digit-serial LDI allpass filter has been implemented to verify this statement. It is shown that retiming can reduce the power consumption with about 20% for small digit-sizes without affecting the throughput of the filter. We also show that introducing a large number of registers in the filter structure will increase the current consumption. This trade-off, between reducing the amount of glitches and the increase in the number of registers, is also considered in this work.

Place, publisher, year, edition, pages
2005.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-4020DOI: 10.1109/ICECS.2005.4633549Scopus ID: 2-s2.0-56749165576ISBN: 978-997261100-1 (print)OAI: oai:DiVA.org:mdh-4020DiVA: diva2:120547
Conference
12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005; Gammarth; 11 December 2005 through 14 December 2005
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2013-01-15Bibliographically approved
In thesis
1. Implementation of digital-serial LDI/LDD allpass filters
Open this publication in new window or tab >>Implementation of digital-serial LDI/LDD allpass filters
2006 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

In this thesis, digit-serial implementation of recursive digital filters is considered. The theories presented can be applied to any recursive digital filter, and in this thesis we study the lossless discrete integrator (LDI) allpass filter. A brief introduction regarding suppression of limit cycles at finite wordlength conditions is given, and an extended stability region, where the second-order LDI allpass filter is free from quantization limit cycles, is presented.

The realization of digit-serial processing elements, i.e., digit-serial adders and multipliers, is studied. A new digit-serial hybrid adder (DSHA) is presented. The adder can be pipelined to the bit level with a short arithmetic critical path, which makes it well suited when implementing high-throughput recursive digital filters.

Two digit-serial multipliers which can be pipelined to the bit level are considered. It is concluded that a digit-serial/parallelmultiplier based on shift-accumulation(DSAAM) is a good candidate when implementing recursive digital systems, mainly due to low latency. Furthermore, our study shows that low latency will lead to higher throughput and lower power consumption.

Scheduling of recursive digit-serial algorithms is studied. It is concluded that implementation issues such as latency and arithmetic critical path are usually required before scheduling considerations can be made. Cyclic scheduling using digit-serial arithmetics is also considered. It is shown that digit-serial cyclic scheduling is very attractive for high-throughput implementations.

Place, publisher, year, edition, pages
Västerås: Institutionen för Datavetenskap och Elektronik, 2006. 154 p.
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 23
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Elektronik
Identifiers
urn:nbn:se:mdh:diva-155 (URN)91-85485-07-1 (ISBN)
Public defence
2006-01-25, Lambda, Västerås, 13:15
Opponent
Available from: 2006-09-06 Created: 2006-09-06

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CiteExportLink to record
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Citation style
  • apa
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Output format
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