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Implementation of high-speed digit-serial LDI allpass filters
Mälardalen University, Department of Computer Science and Electronics.
Mälardalen University, Department of Computer Science and Electronics.
2005 (English)In: Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005, 249-252 p.Conference paper, Published paper (Other academic)
Place, publisher, year, edition, pages
2005. 249-252 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:mdh:diva-4019DOI: 10.1109/ECCTD.2005.1523107Scopus ID: 2-s2.0-33749038013ISBN: 9780780390669 (print)OAI: oai:DiVA.org:mdh-4019DiVA: diva2:120546
Conference
2005 European Conference on Circuit Theory and Design; Cork; Ireland; 28 August 2005 through 2 September 2005;
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2015-07-28Bibliographically approved
In thesis
1. Implementation of digital-serial LDI/LDD allpass filters
Open this publication in new window or tab >>Implementation of digital-serial LDI/LDD allpass filters
2006 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

In this thesis, digit-serial implementation of recursive digital filters is considered. The theories presented can be applied to any recursive digital filter, and in this thesis we study the lossless discrete integrator (LDI) allpass filter. A brief introduction regarding suppression of limit cycles at finite wordlength conditions is given, and an extended stability region, where the second-order LDI allpass filter is free from quantization limit cycles, is presented.

The realization of digit-serial processing elements, i.e., digit-serial adders and multipliers, is studied. A new digit-serial hybrid adder (DSHA) is presented. The adder can be pipelined to the bit level with a short arithmetic critical path, which makes it well suited when implementing high-throughput recursive digital filters.

Two digit-serial multipliers which can be pipelined to the bit level are considered. It is concluded that a digit-serial/parallelmultiplier based on shift-accumulation(DSAAM) is a good candidate when implementing recursive digital systems, mainly due to low latency. Furthermore, our study shows that low latency will lead to higher throughput and lower power consumption.

Scheduling of recursive digit-serial algorithms is studied. It is concluded that implementation issues such as latency and arithmetic critical path are usually required before scheduling considerations can be made. Cyclic scheduling using digit-serial arithmetics is also considered. It is shown that digit-serial cyclic scheduling is very attractive for high-throughput implementations.

Place, publisher, year, edition, pages
Västerås: Institutionen för Datavetenskap och Elektronik, 2006. 154 p.
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 23
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Elektronik
Identifiers
urn:nbn:se:mdh:diva-155 (URN)91-85485-07-1 (ISBN)
Public defence
2006-01-25, Lambda, Västerås, 13:15
Opponent
Available from: 2006-09-06 Created: 2006-09-06

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Cite
Citation style
  • apa
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