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A high-speed low-latency digit-serial hybrid adder
Mälardalen University, Department of Computer Science and Electronics.
Mälardalen University, Department of Computer Science and Electronics.
Linköping University, Sweden.
2004 (English)In: Proceedings - IEEE International Symposium on Circuits and Systems, vol. 3 2004, 2004, 217-220 p.Conference paper, Published paper (Other academic)
Abstract [en]

In this paper, we present a new digit-serial hybrid adder. The adder can be pipelined to the bit-level and is, therefore, well suited for high-speed applications. The main advantage of the proposed adder is that it can be implemented with few pipelining stages. We compare speed, area and power consumption for the proposed adder with a digit-serial carry-look-ahead adder and a digit-serial Ladner-Fisher adder. The results show that the delay of the digit-serial hybrid adder is lower than the other adders studied in this paper for digit-sizes up to d = 12. For these digit-sizes the digit-serial hybrid adder has on average 17% smaller critical path than the digit-serial carry-look-ahead adder and 21% smaller critical path than the digit-serial Ladner-Fisher adder.

Place, publisher, year, edition, pages
2004. 217-220 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:mdh:diva-4017DOI: 10.1109/ISCAS.2004.1328722Scopus ID: 2-s2.0-4344682862ISBN: 0-7803-8251-X (print)OAI: oai:DiVA.org:mdh-4017DiVA: diva2:120544
Conference
2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2015-07-28Bibliographically approved
In thesis
1. Implementation of digital-serial LDI/LDD allpass filters
Open this publication in new window or tab >>Implementation of digital-serial LDI/LDD allpass filters
2006 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

In this thesis, digit-serial implementation of recursive digital filters is considered. The theories presented can be applied to any recursive digital filter, and in this thesis we study the lossless discrete integrator (LDI) allpass filter. A brief introduction regarding suppression of limit cycles at finite wordlength conditions is given, and an extended stability region, where the second-order LDI allpass filter is free from quantization limit cycles, is presented.

The realization of digit-serial processing elements, i.e., digit-serial adders and multipliers, is studied. A new digit-serial hybrid adder (DSHA) is presented. The adder can be pipelined to the bit level with a short arithmetic critical path, which makes it well suited when implementing high-throughput recursive digital filters.

Two digit-serial multipliers which can be pipelined to the bit level are considered. It is concluded that a digit-serial/parallelmultiplier based on shift-accumulation(DSAAM) is a good candidate when implementing recursive digital systems, mainly due to low latency. Furthermore, our study shows that low latency will lead to higher throughput and lower power consumption.

Scheduling of recursive digit-serial algorithms is studied. It is concluded that implementation issues such as latency and arithmetic critical path are usually required before scheduling considerations can be made. Cyclic scheduling using digit-serial arithmetics is also considered. It is shown that digit-serial cyclic scheduling is very attractive for high-throughput implementations.

Place, publisher, year, edition, pages
Västerås: Institutionen för Datavetenskap och Elektronik, 2006. 154 p.
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 23
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Elektronik
Identifiers
urn:nbn:se:mdh:diva-155 (URN)91-85485-07-1 (ISBN)
Public defence
2006-01-25, Lambda, Västerås, 13:15
Opponent
Available from: 2006-09-06 Created: 2006-09-06

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CiteExportLink to record
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Citation style
  • apa
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Output format
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