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Digit-serial implementation of LDI/LDD allpass filters
Mälardalen University, Department of Computer Science and Electronics.
Mälardalen University, Department of Computer Science and Electronics.
Mälardalen University, Department of Computer Science and Electronics.
Linköping University.
2002 (English)Conference paper, Published paper (Other academic)
Abstract [en]

In this paper we study digit-serial implementation of the general-order lossless discrete integrator/differentiator (LDI/LDD) allpass filter structure. In low-power filter implementation, digit-serialcomputation has been shown to be advantageous compared to bit-serial and parallel arithmetics. Thedigit-serial processing elements are obtained using unfolding techniques. The implementation is compared to a corresponding wave digital (WD) implementation. It is shown in an example that a WD realization requires about 60% and 30% more D flip-flops for pipelining and shimming delays, respectively, than the corresponding LDI/LDD implementation. We also study the sample period of the second-order LDI/LDD allpass filter using different digit sizes and conclude that when the filter is scheduled over a number of sample periods we achieve the shortest sample period

Place, publisher, year, edition, pages
2002.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:mdh:diva-4016DOI: 10.1109/ISCAS.2002.1011445ISBN: 0-7803-7448-7 (print)OAI: oai:DiVA.org:mdh-4016DiVA: diva2:120543
Conference
IEEE International Symposium on Circuits and Systems, ISCAS 2002, 26 May 2002-29 May 2002, Phoenix-Scottsdale, AZ, United States
Available from: 2006-09-06 Created: 2006-09-06 Last updated: 2014-05-30Bibliographically approved
In thesis
1. Implementation of digital-serial LDI/LDD allpass filters
Open this publication in new window or tab >>Implementation of digital-serial LDI/LDD allpass filters
2006 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

In this thesis, digit-serial implementation of recursive digital filters is considered. The theories presented can be applied to any recursive digital filter, and in this thesis we study the lossless discrete integrator (LDI) allpass filter. A brief introduction regarding suppression of limit cycles at finite wordlength conditions is given, and an extended stability region, where the second-order LDI allpass filter is free from quantization limit cycles, is presented.

The realization of digit-serial processing elements, i.e., digit-serial adders and multipliers, is studied. A new digit-serial hybrid adder (DSHA) is presented. The adder can be pipelined to the bit level with a short arithmetic critical path, which makes it well suited when implementing high-throughput recursive digital filters.

Two digit-serial multipliers which can be pipelined to the bit level are considered. It is concluded that a digit-serial/parallelmultiplier based on shift-accumulation(DSAAM) is a good candidate when implementing recursive digital systems, mainly due to low latency. Furthermore, our study shows that low latency will lead to higher throughput and lower power consumption.

Scheduling of recursive digit-serial algorithms is studied. It is concluded that implementation issues such as latency and arithmetic critical path are usually required before scheduling considerations can be made. Cyclic scheduling using digit-serial arithmetics is also considered. It is shown that digit-serial cyclic scheduling is very attractive for high-throughput implementations.

Place, publisher, year, edition, pages
Västerås: Institutionen för Datavetenskap och Elektronik, 2006. 154 p.
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 23
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Elektronik
Identifiers
urn:nbn:se:mdh:diva-155 (URN)91-85485-07-1 (ISBN)
Public defence
2006-01-25, Lambda, Västerås, 13:15
Opponent
Available from: 2006-09-06 Created: 2006-09-06

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Publisher's full texthttp://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=21785&arnumber=1011445&count=226&index=174
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CiteExportLink to record
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Citation style
  • apa
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Output format
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