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Designing ASIC/FPGA with Top Down Design Flow and VDHL
Mälardalen University, Department of Computer Science and Engineering.
2001 (English)Licentiate thesis, comprehensive summary (Other scientific)
Place, publisher, year, edition, pages
Institutionen för Datavetenskap , 2001. , p. 41
Series
Mälardalen University Press Licentiate Theses, ISSN 1651-9256 ; 1
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:mdh:diva-112ISBN: 91-88834-82-4 (print)OAI: oai:DiVA.org:mdh-112DiVA, id: diva2:120467
Available from: 2006-02-14 Created: 2006-02-14 Last updated: 2018-01-13

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Total: 152 hits
CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf