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Scheduling Multi-Rate Real-Time Applications on Clustered Many-Core Architectures with Memory Constraints
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1276-3609
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0003-3242-6113
Research and Technology Centre, Robert Bosch, India.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1687-930X
Show others and affiliations
(English)In: 23rd Asia and South Pacific Design Automation Conference ASP-DAC'18Conference paper, Published paper (Refereed)
Abstract [en]

Access to shared memory is one of the main chal- lenges for many-core processors. One group of scheduling strategies for such platforms focuses on the division of tasks’ access to shared memory and code execution. This allows to orchestrate the access to shared local and off-chip memory in a way such that access contention between different compute cores is avoided by design. In this work, an execution framework is introduced that leverages local memory by statically allocating a subset of tasks to cores. This reduces the access times to shared memory, as off-chip memory access is avoided, and in turn improves the schedulability of such systems. A Constrained Programming (CP) formulation is presented to selects the statically allocated tasks and generates the complete system schedule. Evaluations show that the pro- posed approach yields an up to 21% higher schedulability ratio than related work, and a case study demonstrates its applicability to industrial problems.

Keyword [en]
Many-CoreContention-Free ExecutionReal-TimeMemory Constraints
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:mdh:diva-37064OAI: oai:DiVA.org:mdh-37064DiVA: diva2:1154464
Conference
23rd Asia and South Pacific Design Automation Conference ASP-DAC'18, 22 Jan 2018, Jeju Island, South Korea
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and ControlPreView: Developing Predictable Vehicle Software on Multi-core
Available from: 2017-11-02 Created: 2017-11-02 Last updated: 2017-11-02Bibliographically approved
In thesis
1. Consolidating Automotive Real-Time Applications on Many-Core Platforms
Open this publication in new window or tab >>Consolidating Automotive Real-Time Applications on Many-Core Platforms
2017 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Automotive systems have transitioned from basic transportation utilities to sophisticated systems. The rapid increase in functionality comes along with a steep increase in software complexity. This manifests itself in a surge of the number of functionalities as well as the complexity of existing functions. To cope with this transition, current trends shift away from today’s distributed architectures towards integrated architectures, where previously distributed functionality is consolidated on fewer, more powerful, computers. This can ease the integration process, reduce the hardware complexity, and ultimately save costs.

One promising hardware platform for these powerful embedded computers is the many-core processor. A many-core processor hosts a vast number of compute cores, that are partitioned on tiles which are connected by a Network-on-Chip. These natural partitions can provide exclusive execution spaces for different applications, since most resources are not shared among them. Hence, natural building blocks towards temporally and spatially separated execution spaces exist as a result of the hardware architecture.

Additionally to the traditional task local deadlines, automotive applications are often subject to timing constraints on the data propagation through a chain of semantically related tasks. Such requirements pose challenges to the system designer as they are only able to verify them after the system synthesis (i.e. very late in the design process).

In this thesis, we present methods that transform complex timing constraints on the data propagation delay to precedence constraints between individual jobs. An execution framework for the cluster of the many-core is proposed that allows access to cluster external memory while it avoids contention on shared resources by design. A partitioning and configuration of the Network-on-Chip provides isolation between the different applications and reduces the access time from the clusters to external memory. Moreover, methods that facilitate the verification of data propagation delays in each development step are provided. 

Place, publisher, year, edition, pages
Västerås: Malardalen University, 2017
Series
Mälardalen University Press Dissertations, ISSN 1651-4238 ; 246
Keyword
Many-Core, Automotive, Network-on-Chip, Real-Time, Timing analysis
National Category
Embedded Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:mdh:diva-37182 (URN)978-91-7485-359-9 (ISBN)
Public defence
2017-12-19, Kappa, Mälardalens högskola, Västerås, 09:00 (English)
Opponent
Supervisors
Available from: 2017-11-06 Created: 2017-11-02 Last updated: 2017-11-06Bibliographically approved

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Becker, MatthiasMubeen, SaadBehnam, MorisNolte, Thomas

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