mdh.sePublications
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.ORCID iD: 0000-0002-1276-3609
Technische Universität Braunschweig, Germany.
Robert Bosch GmbH, Renningen, Germany.
CISTER/INESC-TEC, ISEP, Portugal.
Show others and affiliations
2017 (English)In: 23rd IEEE Real-Time and Embedded Technology and Applications Symposium RTAS'17, 2017, 101-112 p.Conference paper (Refereed)
Abstract [en]

Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip, which is used for communication among the compute cores via the off- chip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms. In this work, we target a state-of-the-art many-core processor, the Kalray MPPA R . A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis.

Place, publisher, year, edition, pages
2017. 101-112 p.
Keyword [en]
Many-CoreNetwork-on-ChipPartitioningReal-TimeMemory Access
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:mdh:diva-35460DOI: 10.1109/RTAS.2017.32ISBN: 978-1-5090-5269-1 (electronic)OAI: oai:DiVA.org:mdh-35460DiVA: diva2:1108237
Conference
23rd IEEE Real-Time and Embedded Technology and Applications Symposium RTAS'17, 18-21 Apr 2017, Pittsburgh PA, United States
Projects
PREMISE - Predictable Multicore SystemsDPAC - Dependable Platforms for Autonomous systems and Control
Available from: 2017-06-12 Created: 2017-06-12 Last updated: 2017-06-12Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full text

Search in DiVA

By author/editor
Becker, MatthiasBehnam, MorisNolte, Thomas
By organisation
Embedded Systems
Computer Systems

Search outside of DiVA

GoogleGoogle Scholar

Altmetric score

Total: 20 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf