mdh.sePublications
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
ERFAN: Efficient reconfigurable fault-tolerant deflection routing algorithm for 3-D Network-on-Chip
Shahid Beheshti University, Tehran, Iran.
Shahid Beheshti University, Tehran, Iran .
University of Louisiana at Lafayette, Lafayette, United States.
Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Royal Institute of Technology (KTH), Stockholm, Sweden.
Show others and affiliations
2017 (English)In: International System on Chip Conference, IEEE Computer Society, 2017, 306-311 p.Conference paper, Published paper (Refereed)
Abstract [en]

With degradation in transistors dimensions and complication of circuits, Three-Dimensional Network-on-Chip (3-D NoC) is presented as a promising solution in electronic industry. By increasing the number of system components on a chip, the probability of failure will increase. Therefore, proposing fault tolerance mechanisms is an important target in emerging technologies. In this paper, two efficient fault-tolerant routing algorithms for 3-D NoC are presented. The presented algorithms have significant improvement in performance parameters, in exchange for small area overhead. Simulation results show that even with the presence of faults, the network latency is decreased in comparison with state-of-the-art works. In addition, the network reliability is improved reasonably.

Place, publisher, year, edition, pages
IEEE Computer Society, 2017. 306-311 p.
Keyword [en]
3-D NoC, Deflection Routing Algorithm, Fault Tolerance, Reliability, TSV, Distributed computer systems, Fault tolerant computer systems, Network architecture, Programmable logic controllers, Routers, Routing algorithms, Servers, Three dimensional integrated circuits, Deflection routings, Electronic industries, Emerging technologies, Fault tolerance mechanisms, Fault-tolerant routing algorithm, Performance parameters, Probability of failure, Three-dimensional networks, Network-on-chip
National Category
Communication Systems
Identifiers
URN: urn:nbn:se:mdh:diva-35526DOI: 10.1109/SOCC.2016.7905497ISI: 000403576000054Scopus ID: 2-s2.0-85019108151ISBN: 9781509013661 (print)OAI: oai:DiVA.org:mdh-35526DiVA: diva2:1104478
Conference
29th IEEE International System on Chip Conference, SOCC 2016; Seattle; United States; 6-9 September 2016.
Available from: 2017-06-01 Created: 2017-06-01 Last updated: 2017-11-10Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Search in DiVA

By author/editor
Daneshtalab, Masoud
By organisation
Embedded Systems
Communication Systems

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 5 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf